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description the 7641 group is the 8-bit microcomputer based on the 7600 series core (740 family core compatible) technology. the 7641 group is designed for pc peripheral devices, including the usb, dmac, serial i/o, uart, timer, master cpu bus interface and so on. features power source voltage at 24 mhz oscillation frequency, = 12 mhz ......... 4.15 to 5.25 v at 24 mhz oscillation frequency, = 6 mhz ........... 3.00 to 3.60 v program/erase voltage .................................. v cc = 4.50 v to 5.25 v, or 3.00 v to 3.60 v .................................................................. v pp = 4.50 v to 5.25 v at 24 mhz oscillation frequency, = 6 mhz (see table 25.) memory size flash rom .................................................................... 32 kbytes ram ............................................................................. 2.5 kbytes flash memory mode ....................................................... 3 modes parallel i/o mode standard serial i/o mode cpu rewrite mode programming method ....................... programming in unit of byte erasing method batch erasing block erasing program/erase control by software command command number ................................................... 6 commands number of times for programming/erasing ............................. 100 rom code protection available in parallel i/o mode and standard serial i/o mode operating temperature range (at programming/erasing) .............. ...................................................................... normal temperature application audio, musical instrument, printer, scanner, modem, other pc pe- ripheral devices notes the flash memory version cannot be used for application embed- ded in the mcu card. 7641 group single-chip 8-bit cmos microcomputer rej03b0191-0400 rev.4.00 aug 28, 2006 rev.4.00 aug 28, 2006 page 1 of 135 rej03b0191-0400
7641 group rev.4.00 aug 28, 2006 page 2 of 135 rej03b0191-0400 pin configuration (top view) fig. 1 m37641m8-xxxfp, m37641f8fp pin configuration p 7 4 / o b f 1 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 79 8 0 p6 1 /dq 1 p5 6 /r(e) p 5 5 / a 0 p5 3 /ibf 0 p5 2 /obf 0 cnv ss /v pp reset av cc av ss p4 4 /cntr 1 p 8 7 / r t s 1 p 8 6 / c t s 1 v cc p5 0 /x cin v ss x in x out p5 1 /t out /x cout lpf p 8 5 / u r x d 1 p 8 4 / u t x d 1 p 3 2 p 3 1 m 3 7 6 4 1 m 8 - x x x f p m 3 7 6 4 1 f 8 f p p6 0 /dq 0 p5 7 /w/(r/w) p 5 4 / s 0 2 1 2 2 2 3 2 4 p4 3 /cntr 0 p4 2 /int 1 p4 1 /int 0 p4 0 /edma 6 1 6 2 6 3 6 4 p 8 3 / r t s 2 / s t x d p 8 2 / c t s 2 / s r x d p 8 1 / u r x d 2 / s c l k p 8 0 / u t x d 2 / s r d y p 3 7 / r d p 3 6 / w r p 3 5 / s y n c o u t p 3 4 / o u t p 3 3 / d m a o u t p 3 0 / r d y p 1 7 / a b 1 5 p 1 6 / a b 1 4 p 1 5 / a b 1 3 p 1 4 / a b 1 2 p 1 3 / a b 1 1 p 1 2 / a b 1 0 p 1 1 / a b 9 p 1 0 / a b 8 p 0 7 / a b 7 p 0 6 / a b 6 p 0 5 / a b 5 p 0 4 / a b 4 p 0 3 / a b 3 p 0 2 / a b 2 p 0 1 / a b 1 p 0 0 / a b 0 p 2 7 / d b 7 p 2 6 / d b 6 p 2 5 / d b 5 p 2 4 / d b 4 p 2 3 / d b 3 p 2 2 / d b 2 p 2 1 / d b 1 p 2 0 / d b 0 p 7 3 / i b f 1 / h l d a p 7 2 / s 1 p 7 1 / h o l d p 7 0 / s o f u s b d + u s b d - e x t . c a p v s s v c c p 6 7 / d q 7 p 6 6 / d q 6 p 6 5 / d q 5 p 6 4 / d q 4 p6 3 /dq 3 p 6 2 / d q 2 p 7 4 / o b f 1 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 78 79 80 p 6 1 / d q 1 p5 6 /r(e) p 5 5 / a 0 p5 3 /ibf 0 p5 2 /obf 0 c n v s s / v p p reset av cc av ss p 4 4 / c n t r 1 p 8 7 / r t s 1 p8 6 /cts 1 v cc p5 0 /x cin v ss x in x out p5 1 /t out /x cout l p f p 8 5 / u r x d 1 p 8 4 / u t x d 1 p 3 2 p 3 1 m37641m8-xxxhp m37641f8hp p 6 0 / d q 0 p 5 4 / s 0 2 1 2 2 23 24 p 4 3 / c n t r 0 p 4 2 / i n t 1 p 4 1 / i n t 0 6 1 6 2 6 3 6 4 p 8 3 / r t s 2 / s t x d p 8 2 / c t s 2 / s r x d p 8 1 / u r x d 2 / s c l k p 8 0 / u t x d 2 / s r d y p 3 7 / r d p 3 6 / w r p 3 5 / s y n c o u t p 3 4 / o u t p 3 3 / d m a o u t p 3 0 / r d y p 1 7 / a b 1 5 p 1 6 / a b 1 4 p 1 5 / a b 1 3 p 1 4 / a b 1 2 p 1 3 / a b 1 1 p 1 2 / a b 1 0 p 1 1 / a b 9 p 1 0 / a b 8 p 0 7 / a b 7 p 0 6 / a b 6 p 0 5 / a b 5 p 0 4 / a b 4 p 0 3 / a b 3 p 0 2 / a b 2 p 0 1 / a b 1 p 0 0 / a b 0 p 2 7 / d b 7 p 2 6 / d b 6 p 2 5 / d b 5 p 2 4 / d b 4 p 2 3 / d b 3 p 2 2 / d b 2 p2 1 /db 1 p2 0 /db 0 u s b d + u s b d - e x t . c a p v s s v c c p 6 7 / d q 7 p 6 6 / d q 6 p 6 5 / d q 5 p 6 4 / d q 4 p 6 3 / d q 3 p 6 2 / d q 2 p 4 0 / e d m a p 7 1 / h o l d p 7 0 / s o f p 5 7 / w / ( r / w ) p7 2 /s 1 p 7 3 / i b f 1 / h l d a package type : prqp0080gb-a (80p6n-a) package type : plqp0080kb-a (80p6q-a) fig. 2 m37641m8-xxxhp, m37641f8hp pin configuration
7641 group rev.4.00 aug 28, 2006 page 3 of 135 rej03b0191-0400 functional block diagram (package: prqp0080gb-a) fig. 3 functional block diagram t out c p u a x y s pc h pc l ps reset v cc v ss r o m r a m 10 16 13 p2(8) i/o port p0 p0(8) p1(8) p3(8) p5(8) 49 50 51 52 53 54 55 56 41 42 43 44 45 46 47 48 57 58 59 60 61 62 63 64 33 34 35 36 37 38 39 40 p6(8) 20 21 22 23 24 x in x out timer x (16) timer y (16) timer 1 (8) timer 2 (8) timer 3 (8) 14 15 75 76 77 78 79 80 12 p7(5) 65 66 67 69 68 p8(8) 25 26 27 28 29 30 31 32 d+ d- cntr 1 , cntr 0 usb v cc 74 v ss 73 cnv ss 9 uart1 (8) uart2 (8) sof 70 71 3456781112 w(r/w) r(e),a 0 s 0 ,ibf 0 obf 0 int 1 , int 0 p4(5) dma [dma out ] ext.cap 72 lpf 18 av ss 19 dq 0 to dq 7 s 1 , ibf 1 obf 1 t out 3 6 [ out ] 35 40 24 33 34 [edma] [rd] [wr] [sync out ][rdy] 66 [hlda] 68 [hold] 17 avcc main clock input main clock output clock generating circuit reset input x c in x cout serial i/o (8) master cpu bus interface x c in key input i/o port p1 i/o port p2 i/o port p3 i/o port p4 i/o port p5 i/o port p6 i/o port p7 i/o port p8 reset
7641 group rev.4.00 aug 28, 2006 page 4 of 135 rej03b0191-0400 p5 0 /x cin , p5 1 /t out / x cout , p5 2 /obf 0 , p5 3 /ibf 0 , p5 4 /s 0 , p5 5 /a 0 , p5 6 /r(e), p5 7 /w(r/w) ? apply 4.15 v C 5.25 v for 5 v version or 3.00 v C 3.60 v for 3 v version to the vcc pin. apply 0 v to the vss pin. ? this controls the mcu operating mode. connect this pin to vss. if connecting this pin to vcc, the internal rom is inhibited. in the flash memory version this pin functions as a v pp power supply input pin. ? these pins are the power supply inputs for analog circuitry. ? reset input pin for active l. ? connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. ? if an external clock is used, connect the clock source to the x in pin and leave the x out pin open. ? loop filter for the frequency synthesizer. ? it is a capacitor connection pin for built-in dc-dc converter. at vcc=5 v, use built-in dc-dc converter by permitting a usb line driver and connect a capacitor. refer to "notes on use" for details. built-in dc- dc converter cannot be used at vcc = 3.3 v. supply 3.3v power supply to this pin from the externals. ? usb d+ voltage signal port. connect a 27 to 33 ? (recommended) resistor in series. ? usb d- voltage signal port. connect a 27 to 33 ? (recommended) resistor in series. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when connecting an external memory, these function as the address bus. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when connecting an external memory, these function as the address bus. ? key-on wake-up interrupt input pin v cc , v ss cnvss/v pp avss/avcc reset x in x out lpf ext. cap. usb d+ usb d- p0 0 /ab 0 C p0 7 /ab 7 name power source cnvss analog power supply reset input clock input clock output lpf 3.3 v line power supply usb d+ usb d- function except a port function pin description table 1 pin description (1) function p1 0 /ab 8 C p1 7 /ab 15 p2 0 /db 0 C p2 7 /db 7 ? 8-bit i/o port. ? cmos compatible input level or vihl input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when connecting an external memory, these function as the data bus. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when connecting an external memory, these function as the control bus. p3 0 /rdy, p3 1 , p3 2 , p3 3 /dma out , p3 4 / out , p3 5 /sync out , p3 6 /wr, ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when connecting an external memory, these function as the control bus. ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when enabling the master cpu bus interface function, cmos or ttl input level can be selected as an input. i/o port p0 i/o port p1 i/o port p2 i/o port p3 (see remarks.) ? external memory control pin i/o port p4 p3 7 /rd p4 0 /edma, p4 1 /int 0 , p4 2 /int 1 , p4 3 /cntr 0 , p4 4 /cntr 1 ? external memory control pin ? external interrupt pin ? timer x, timer y pin ? sub-clock generating input pin ? timers 1, 2 pulse output pins ? sub-clock generating output pin ? master cpu bus interface pin pin
7641 group rev.4.00 aug 28, 2006 page 5 of 135 rej03b0191-0400 pin name function except a port function function table 2 pin description (2) p6 0 /dq 0 C p6 7 /dq 7 i/o port p5 ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? when enabling the bus interface function, cmos or ttl input level can be selected as its input. ? 5-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually programmed as either input or output. ? master cpu bus interface pin p7 0 /sof, p7 1 /hold, p7 2 /s 1 , p7 3 /ibf 1 / hlda, p7 4 /obf 1 p8 0 /utxd 2 / srdy, p8 1 /urxd 2 / sclk, p8 2 /cts 2 / srxd, p8 3 /rts 2 / stxd, p8 4 /utxd 1 , p8 5 /urxd 1 , p8 6 /cts 1 , p8 7 /rts 1 i/o port p6 i/o port p7 i/o port p8 ? 8-bit i/o port. ? cmos compatible input level. ? cmos 3-state output structure. ? i/o direction register allows each pin to be individually pro- grammed as either input or output. ? usb function pin ? master cpu bus interface pin ? serial i/o pin ? uart2 pin ? uart1 pin remarks ? dma out pin if externally detecting the timing of dma execution, use the signal from this pin. it is h level during dma transferring. this signal is valid in the memory expansion and microprocessor modes. ? sync out pin if externally detecting the timing of op code fetch, use the signal from this pin. this signal is valid in the memory expansion and microprocessor modes.
7641 group rev.4.00 aug 28, 2006 page 6 of 135 rej03b0191-0400 part numbering fig. 4 part numbering m37641 m 8 C xxx fp product rom size/ 8: 32768 bytes the first 128 bytes and the last 4 bytes of rom are reserved areas; they cannot be used. in the flash memory version, these areas can be used for program and erase. memory type m: mask rom version f: flash memory version ram size m37641m8 : 1024 bytes m37641f8 : 2560 bytes package type fp: prqp0080gb-a package hp: plqp0080kb-a package rom number omitted in flash memory version. ? standard omitted in flash memory version. flash memory size
7641 group rev.4.00 aug 28, 2006 page 7 of 135 rej03b0191-0400 group expansion mitsubishi plans to expand the 7641 group as follows. memory type supports for mask rom and flash memory versions. memory size rom size ......................................................................... 32 kbytes ram size ........................................................... 1024 to 2560 bytes memory expansion plan fig. 5 memory expansion plan currently planning products are listed below. as of aug. 2006 package prqp0080gb-a plqp0080kb-a prqp0080gb-a plqp0080kb-a product name m37641m8-xxxfp m37641m8-xxxhp m37641f8fp m37641f8hp rom size (bytes) rom size for user in ( ) 32768 (32636) ram size (bytes) 1024 table 3 support products mask rom version remarks packages prqp0080gb-a ......................... 0.8 mm-pitch plastic molded qfp plqp0080kb-a ........................ 0.5 mm-pitch plastic molded lqfp r o m e x t e r n a l 6 0 k 4 8 k 32 k 2 8 k 2 4 k 20 k 16 k 1 2 k 8 k 384 512 640 768 896 1024 1152 1280 1408 1536 2048 3072 4032 rom size (bytes) r a m s i z e ( b y t e s ) m37641m 8 m 3 7 6 4 1 f 8 32768 2560 flash memory version
7641 group rev.4.00 aug 28, 2006 page 8 of 135 rej03b0191-0400 functional description central processing unit (cpu) the 7641 group uses the standard 7600 series instruction set. refer to the 7600 series software manual for details on the instruction set. the 7600 series has an upward compatible instruction set, of which instruction execution cycles are shortened, for 740 series. [accumulator (a)] the accumulator is an 8-bit register. data operations such as data transfer, etc., are executed mainly through the accumulator. [index register x (x)] the index register x is an 8-bit register. in the index addressing modes, the value of the operand is added to the contents of register x and specifies the real address. [index register y (y)] the index register y is an 8-bit register. in partial instruction, the value of the operand is added to the contents of register y and specifies the real address. [stack pointer (s)] the stack pointer is an 8-bit register used during subroutine calls and interrupts. this register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. the low-order 8 bits of the stack address are determined by the con- tents of the stack pointer. the high-order 8 bits of the stack address are determined by the stack page selection bit. if the stack page selection bit is 0 , the high-order 8 bits becomes 00 16 . if the stack page selection bit is 1 , the high-order 8 bits becomes 01 16 . the operations of pushing register contents onto the stack and pop- ping them from the stack are shown in figure 7. store registers other than those described in figure 7 with program when the user needs them during interrupts or subroutine calls. [program counter (pc)] the program counter is a 16-bit counter consisting of two 8-bit regis- ters pc h and pc l . it is used to indicate the address of the next in- struction to be executed. fig. 6 7600 series cpu register structure a accumulator b7 b7 b7 b7 b0 b7 b8 b15 b0 b7 b0 b0 b0 b0 x index register x y index register y s stack pointer pc l program counter pc h n v t b d i z c processor status register (ps) carry flag zero flag interrupt disable flag decimal mode flag break flag index x mode flag overflow flag negative flag
7641 group rev.4.00 aug 28, 2006 page 9 of 135 rej03b0191-0400 table 4 push and pop instructions of accumulator or processor status register accumulator processor status register push instruction to stack pha php pop instruction from stack pla plp fig. 7 register push and pop at interrupt generation and subroutine call n o t e : c o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t i n t e r r u p t e n a b l e f l a g i s 1 e x e c u t e j s r o n - g o i n g r o u t i n e m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) e x e c u t e r t s ( p c l )m ( s ) ( s ) ( s ) C 1 ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) s u b r o u t i n e p o p re t u r n a d d r e s s f r o m s t a c k p u s h r e t u r n a d d r e s s o n s t a c k m ( s )( p s ) e x e c u t e r t i ( p s )m ( s ) ( s ) ( s ) C 1 ( s ) ( s ) + 1 i n t e r r u p t s e r v i c e r o u t i n e p o p c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k m ( s )( p c h ) ( s ) ( s ) C 1 m ( s )( p c l ) ( s ) ( s ) C 1 ( p c l )m ( s ) ( s ) ( s ) + 1 ( s ) ( s ) + 1 ( p c h )m ( s ) p o p r e t u r n a d d r e s s f r o m s t a c k i f l a g i s s e t f r o m 0 t o 1 f e t c h t h e j u m p v e c t o r p u s h r e t u r n a d d r e s s o n s t a c k p u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k i n t e r r u p t r e q u e s t ( n o t e ) i n t e r r u p t d i s a b l e f l a g i s 0
7641 group rev.4.00 aug 28, 2006 page 10 of 135 rej03b0191-0400 [processor status register (ps)] the processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic opera- tion and 3 flags which decide mcu operation. branch operations can be performed by testing the carry (c) flag , zero (z) flag, overflow (v) flag, or the negative (n) flag. in decimal mode, the z, v, n flags are not valid. ? bit 0: carry flag (c) the c flag contains a carry or borrow generated by the arithmetic logic unit (alu) immediately after an arithmetic operation. it can also be changed by a shift or rotate instruction. ? bit 1: zero flag (z) the z flag is set if the result of an immediate arithmetic operation or a data transfer is 0 , and cleared if the result is anything other than 0 . ? bit 2: interrupt disable flag (i) the i flag disables all interrupts except for the interrupt generated by the brk instruction. interrupts are disabled when the i flag is 1 . ? bit 3: decimal mode flag (d) the d flag determines whether additions and subtractions are executed in binary or decimal. binary arithmetic is executed when this flag is 0 ; decimal arithmetic is executed when it is 1 . decimal correction is automatic in decimal mode. only the adc ? bit 4: break flag (b) the b flag is used to indicate that the current interrupt was generated by the brk instruction. the brk flag in the processor status register is always 0 . when the brk instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to 1 . ? bit 5: index x mode flag (t) when the t flag is 0 , arithmetic operations are performed between accumulator and memory. when the t flag is 1 , direct arithmetic operations and direct data transfers are enabled between memory locations. ? bit 6: overflow flag (v) the v flag is used during the addition or subtraction of one byte of signed data. it is set if the result exceeds +127 to -128. when the bit instruction is executed, bit 6 of the memory location operated on by the bit instruction is stored in the overflow flag. ? bit 7: negative flag (n) the n flag is set if the result of an arithmetic operation or data transfer is negative. when the bit instruction is executed, bit 7 of the memory location operated on by the bit instruction is stored in the negative flag. table 5 set and clear instructions of each bit of processor status register set instruction clear instruction c flag sec clc z flag C C i flag sei cli d flag sed cld b flag C C t flag set clt v flag C clv n flag C C
7641 group rev.4.00 aug 28, 2006 page 11 of 135 rej03b0191-0400 [cpu mode registers a, b (cpuma, cpumb)] 0000 16 , 0001 16 the cpu mode register contains the stack page select bit and the cpu operating mode select bit and so on. the cpu mode registers are allocated at address 0000 16 , 0001 16 . fig. 8 structure of cpu mode register do not use the microprocessor mode in the flash memory version. cpu mode register a (address 0000 16 ) cpma p r o c e s s o r m o d e b i t s b 1 b 0 0 0 : s i n g l e - c h i p m o d e 0 1 : m e m o r y e x p a n s i o n m o d e 1 0 : m i c r o p r o c e s s o r m o d e ( n o t e 1 ) 1 1 : n o t a v a i l a b l e s t a c k p a g e s e l e c t b i t 0 : p a g e 0 1 : p a g e 1 f i x t o 1 . s u b - c l o c k ( x c i n - x c o u t ) c o n t r o l b i t 0 : s t o p p e d 1 : o s c i l l a t i n g m a i n c l o c k ( x i n - x o u t ) c o n t r o l b i t 0 : o s c i l l a t i n g 1 : s t o p p e d i n t e r n a l s y s t e m c l o c k s e l e c t b i t ( n o t e 2 ) 0 : e x t e r n a l c l o c k ( x i n - x o u t o r x c i n - x c o u t ) 1 : f s y n e x t e r n a l c l o c k s e l e c t b i t 0 : x i n - x o u t 1 : x c i n - x c o u t b0 b7 1 notes 1: this is not available in the flash memory version. 2: when (cpma 6, 7) = (0, 0), the internal system clock can be selected between f(x in ) or f(x in )/2 by ccr7. the internal clock is the internal system clock divided by 2. cpu mode register b (address 0001 16 ) cpmb slow memory wait select bits b1b0 0 0: no wait 0 1: one-time wait 1 0: two-time wait 1 1: three-time wait slow memory wait mode select bits b3b2 0 0: software wait 0 1: not available 1 0: rdy wait 1 1: software wait plus rdy input anytime wait expanded data memory access bit 0: edma output disabled 1: edma output enabled hold function enable bit 0: hold function disabled 1: hold function enabled resereved bit ( 0 at read/write) fix to 1 . b 0 b 7 1 0
7641 group rev.4.00 aug 28, 2006 page 12 of 135 rej03b0191-0400 memory special function register (sfr) area the special function register area in the zero page contains control registers such as i/o ports and timers. ram ram is used for data storage and for stack area of subroutine calls and interrupts. rom the first 128 bytes and the last 4 bytes of rom are reserved for device testing and the rest is user area for storing programs. in the flash memory version, program and erase can be performed in the reserved area. interrupt vector area the interrupt vector area contains reset and interrupt vectors. zero page access to this area with only 2 bytes is possible in the zero page addressing mode. special page access to this area with only 2 bytes is possible in the special page addressing mode. refer to page 74 for the memory map of memory expansion and microprocessor modes. fig. 9 memory map diagram 1 0 2 4 2 5 6 0 046 f 16 0a6f 16 r a m a r e a r a m s i z e ( b y t e s ) a d d r e s s x x x x 1 6 0000 16 0070 16 ff 00 16 f f c a 1 6 fffc 16 ffff 16 x x x x 1 6 8 0 0 0 1 6 8 0 8 0 1 6 ram rom size: 32768 bytes s f r a r e a n ot use d i n t e r r u p t v e c t o r a r e a r e s e r v e d r o m a r e a ( 1 2 8 b y t e s ) z ero page s pec i a l page r eserve d rom area 0100 16 1000 16 r eserve d area ( n ote 1 ) s f r a r e a ( n ote 2 ) ffc 9 16 m 3 7 6 4 1 m 8 m 3 7 6 4 1 f 8 n o t e s1 : r e s e r v e d a r e a i n m 3 7 6 4 1 f 8 . 2 : s f r a r e a i n m 3 7 6 4 1 f 8 .
7641 group rev.4.00 aug 28, 2006 page 13 of 135 rej03b0191-0400 fig. 10 memory map of special function register (sfr) c p u m o d e r e g i s t e r a ( c p u a ) c p u m o d e r e g i s t e r b ( c p u b ) i n t e r r u p t r e q u e s t r e g i s t e r a ( i r e q a ) i n t e r r u p t r e q u e s t r e g i s t e r b ( i r e q b ) i n t e r r u p t r e q u e s t r e g i s t e r c ( i r e q c ) i n t e r r u p t c o n t r o l r e g i s t e r a ( i c o n a ) i n t e r r u p t c o n t r o l r e g i s t e r b ( i c o n b ) i n t e r r u p t c o n t r o l r e g i s t e r c ( i c o n c ) p o r t p 0 ( p 0 ) p o r t p 0 d i r e c t i o n r e g i s t e r ( p 0 d ) p o r t p 1 ( p 1 ) p o r t p 1 d i r e c t i o n r e g i s t e r ( p 1 d ) p o r t p 2 ( p 2 ) p o r t p 2 d i r e c t i o n r e g i s t e r ( p 2 d ) p o r t p 3 ( p 3 ) p o r t p 3 d i r e c t i o n r e g i s t e r ( p 3 d ) p o r t c o n t r o l r e g i s t e r ( p t c ) i n t e r r u p t p o l a r i t y s e l e c t r e g i s t e r ( i p o l ) p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r ( p u p 2 ) u s b c o n t r o l r e g i s t e r ( u s b c ) p o r t p 6 ( p 6 ) p o r t p 6 d i r e c t i o n r e g i s t e r ( p 6 d ) p o r t p 5 ( p 5 ) p o r t p 5 d i r e c t i o n r e g i s t e r ( p 5 d ) p o r t p 4 ( p 4 ) p o r t p 4 d i r e c t i o n r e g i s t e r ( p 4 d ) p o r t p 7 ( p 7 ) p o r t p 7 d i r e c t i o n r e g i s t e r ( p 7 d ) p o r t p 8 ( p 8 ) p o r t p 8 d i r e c t i o n r e g i s t e r ( p 8 d ) r e s e r e v e d ( n o t e 1 ) c l o c k c o n t r o l r e g i s t e r ( c c r ) t i m e r x l ( t x l ) t i m e r x h ( t x h ) t i m e r y l ( t y l ) t i m e r y h ( t y h ) t i m e r 1 ( t 1 ) t i m e r 2 ( t 2 ) t i m e r 3 ( t 3 ) t i m e r x m o d e r e g i s t e r ( t x m ) t i m e r y m o d e r e g i s t e r ( t y m ) t i m e r 1 2 3 m o d e r e g i s t e r ( t 1 2 3 m ) s e r i a l i / o s h i f t r e g i s t e r ( s i o s h t ) s e r i a l i / o c o n t r o l r e g i s t e r 1 ( s i o c o n 1 ) s e r i a l i / o c o n t r o l r e g i s t e r 2 ( s i o c o n 2 ) s p e c i a l c o u n t s o u r c e g e n e r a t o r 1 ( s c s g 1 ) s p e c i a l c o u n t s o u r c e g e n e r a t o r 2 ( s c s g 2 ) s p e c i a l c o u n t s o u r c e m o d e r e g i s t e r ( s c s g m ) u a r t 1 m o d e r e g i s t e r ( u 1 m o d ) u a r t 1 b a u d r a t e g e n e r a t o r ( u 1 b r g ) u a r t 1 s t a t u s r e g i s t e r ( u 1 s t s ) u a r t 1 c o n t r o l r e g i s t e r ( u 1 c o n ) u a r t 1 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 1 ( u 1 t r b 1 ) u a r t 1 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 2 ( u 1 t r b 2 ) u a r t 1 r t s c o n t r o l r e g i s t e r ( u 1 r t s c ) r e s e r e v e d ( n o t e 1 ) 0 0 0 0 1 6 0 0 0 1 1 6 0 0 0 3 1 6 0 0 0 4 1 6 0 0 0 2 1 6 0 0 0 5 1 6 0 0 0 6 1 6 0 0 0 7 1 6 0 0 0 8 1 6 0009 16 0 0 0 a 1 6 0 0 0 b 1 6 0 0 0 c 1 6 0 0 0 d 1 6 0 0 0 e 1 6 0 0 0 f 1 6 0 0 1 0 1 6 0 0 1 1 1 6 0 0 1 2 1 6 0013 16 0014 16 0015 16 0 0 1 6 1 6 0 0 1 7 1 6 0 0 1 8 1 6 0 0 1 9 1 6 0 0 1 a 1 6 0 0 1 b 1 6 0 0 1 c 1 6 001d 16 0 0 1 e 1 6 0 0 1 f 1 6 0 0 2 0 1 6 0021 16 0 0 2 2 1 6 0 0 2 3 1 6 0 0 2 4 1 6 0025 16 0 0 2 6 1 6 0027 16 0028 16 0029 16 0 0 2 a 1 6 0 0 2 b 1 6 0 0 2 c 1 6 002d 16 002e 16 0 0 2 f 1 6 0030 16 0 0 3 1 1 6 0 0 3 2 1 6 0 0 3 3 1 6 0034 16 0 0 3 5 1 6 0 0 3 6 1 6 0037 16 u a r t 2 m o d e r e g i s t e r ( u 2 m o d ) u a r t 2 b a u d r a t e g e n e r a t o r ( u 2 b r g ) u a r t 2 s t a t u s r e g i s t e r ( u 2 s t s ) u a r t 2 c o n t r o l r e g i s t e r ( u 2 c o n ) u a r t 2 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 1 ( u 2 t r b 1 ) u a r t 2 t r a n s m i t / r e c e i v e b u f f e r r e g i s t e r 2 ( u 2 t r b 2 ) u a r t 2 r t s c o n t r o l r e g i s t e r ( u 2 r t s c ) d m a c i n d e x a n d s t a t u s r e g i s t e r ( d m a i s ) d m a c c h a n n e l x m o d e r e g i s t e r 1 ( d m a x 1 ) d m a c c h a n n e l x m o d e r e g i s t e r 2 ( d m a x 2 ) d m a c c h a n n e l x s o u r c e r e g i s t e r l o w ( d m a x s l ) d m a c c h a n n e l x s o u r c e r e g i s t e r h i g h ( d m a x s h ) d m a c c h a n n e l x d e s t i n a t i o n r e g i s t e r l o w ( d m a x d l ) d m a c c h a n n e l x d e s t i n a t i o n r e g i s t e r h i g h ( d m a x d h ) d m a c c h a n n e l x t r a n s f e r c o u n t r e g i s t e r l o w ( d m a x c l ) d m a c c h a n n e l x t r a n s f e r c o u n t r e g i s t e r h i g h ( d m a x c h ) d a t a b u s b u f f e r r e g i s t e r 0 ( d b b 0 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 0 ( d b b s 0 ) d a t a b u s b u f f e r c o n t r o l r e g i s t e r 0 ( d b b c 0 ) r e s e r e v e d ( n o t e 1 ) d a t a b u s b u f f e r r e g i s t e r 1 ( d b b 1 ) d a t a b u s b u f f e r s t a t u s r e g i s t e r 1 ( d b b s 1 ) d a t a b u s b u f f e r c o n t r o l r e g i s t e r 1 ( d b b c 1 ) r e s e r e v e d ( n o t e 1 ) u s b a d d r e s s r e g i s t e r ( u s b a ) u s b p o w e r m a n a g e m e n t r e g i s t e r ( u s b p m ) u s b i n t e r r u p t s t a t u s r e g i s t e r 1 ( u s b i s 1 ) u s b i n t e r r u p t s t a t u s r e g i s t e r 2 ( u s b i s 2 ) u s b i n t e r r u p t e n a b l e r e g i s t e r 1 ( u s b i e 1 ) u s b i n t e r r u p t e n a b l e r e g i s t e r 2 ( u s b i e 2 ) u s b f r a m e n u m b e r r e g i s t e r l o w ( u s b s o f l ) u s b f r a m e n u m b e r r e g i s t e r h i g h ( u s b s o f h ) u s b e n d p o i n t i n d e x r e g i s t e r ( u s b i n d e x ) u s b e n d p o i n t x i n c o n t r o l r e g i s t e r ( i n _ c s r ) u s b e n d p o i n t x o u t c o n t r o l r e g i s t e r ( o u t _ c s r ) u s b e n d p o i n t x i n m a x . p a c k e t s i z e r e g i s t e r ( i n _ m a x p ) u s b e n d p o i n t x o u t m a x . p a c k e t s i z e r e g i s t e r ( o u t _ m a x p ) u s b e n d p o i n t x o u t w r i t e c o u n t r e g i s t e r l o w ( w r t _ c n t l ) u s b e n d p o i n t x o u t w r i t e c o u n t r e g i s t e r h i g h ( w r t _ c n t h ) u s b e n d p o i n t f i f o m o d e r e g i s t e r ( u s b f i f o m r ) u s b e n d p o i n t 0 f i f o ( u s b f i f o 0 ) u s b e n d p o i n t 1 f i f o ( u s b f i f o 1 ) u s b e n d p o i n t 2 f i f o ( u s b f i f o 2 ) u s b e n d p o i n t 3 f i f o ( u s b f i f o 3 ) u s b e n d p o i n t 4 f i f o ( u s b f i f o 4 ) r e s e r e v e d ( n o t e 1 ) r e s e r e v e d ( n o t e 1 ) r e s e r e v e d ( n o t e 1 ) r e s e r e v e d ( n o t e 1 ) r e s e r e v e d ( n o t e 1 ) f l a s h m e m o r y c o n t r o l r e g i s t e r ( f m c r ) ( n o t e 2 ) r e s e r e v e d ( n o t e 1 ) f r e q u e n c y s y n t h e s i z e r c o n t r o l r e g i s t e r ( f s c ) f r e q u e n c y s y n t h e s i z e r m u l t i p l y r e g i s t e r 1 ( f s m 1 ) f r e q u e n c y s y n t h e s i z e r m u l t i p l y r e g i s t e r 2 ( f s m 2 ) f r e q u e n c y s y n t h e s i z e r d i v i d e r e g i s t e r ( f s d ) 0038 16 0 0 3 9 1 6 0 0 3 b 1 6 0 0 3 c 1 6 0 0 3a 1 6 0 0 3 d 1 6 0 0 3 e 1 6 0 0 3 f 1 6 0 0 4 0 1 6 0041 16 0 0 4 2 1 6 0 0 4 3 1 6 0 0 4 4 1 6 0 0 4 5 1 6 0 0 4 6 1 6 0 0 4 7 1 6 0 0 4 8 1 6 0 0 4 9 1 6 0 0 4 a 1 6 0 0 4 b 1 6 004c 16 004d 16 0 0 4 e 1 6 0 0 4 f 1 6 0 0 5 0 1 6 0 0 5 1 1 6 0 0 5 2 1 6 0053 16 0054 16 0 0 5 5 1 6 0 0 5 6 1 6 0 0 5 7 1 6 0 0 5 8 1 6 0059 16 0 0 5 a 1 6 0 0 5 b 1 6 0 0 5 c 1 6 005d 16 0 0 5 e 1 6 005f 16 0060 16 0061 16 0 0 6 2 1 6 0 0 6 3 1 6 0 0 6 4 1 6 0065 16 0066 16 0 0 6 7 1 6 0 0 6 8 1 6 0069 16 006a 16 0 0 6 b 1 6 006c 16 0 0 6 d 1 6 0 0 6 e 1 6 006f 16 f f c 9 1 6 r o m c o d e p r o t e c t c o n t r o l r e g i s t e r ( r o m c p ) ( n o t e 3 ) notes 1 : do not write any data to this addresses, because these areas are reserved. 2 : this area is reserved in the mask rom version. 3 : this area is on the rom in the mask rom version.
7641 group rev.4.00 aug 28, 2006 page 14 of 135 rej03b0191-0400 i/o ports direction registers the i/o ports p0 C p8 have direction registers which determine the input/output direction of each individual pin. each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. when 0 is written to the bit corresponding to a pin, that pin be- comes an input pin. when 1 is written to that bit, that pin becomes an output pin. if data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. pins set to input are float- ing. if a pin set to input is written to, only the port output latch is written to and the pin remains floating. slew rate control by setting bits 0 to 5 of the port control register (address 0010 16 ) to 1 , slew rate control is enabled. vihl or cmos level can be used as a port p2 input level; cmos or ttl level can be used as an input level of master cpu bus interface. pull-up control by setting the port p2 pull-up control register (address 0012 16 ), pull- up of each pin of port p2 can be controlled with a program. however, the contents of port p2 pull-up control register do not affect ports programmed as the output ports but as the input ports. fig. 11 structure of port control and port p2 pull-up control registers port control register (address 0010 16 ) ptc port p0 to p3 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p4 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p5 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p6 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p7 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p8 slew rate control bit ( note 1 ) 0: disabled 1: enabled port p2 input level select bit 0: reduced vihl level input ( note 2 ) 1: cmos level input master cpu bus input level select bit 0: cmos level input 1: ttllevel input notes 1 : the slew rate function can reduce di/dt by modifying an internal buffer structure. 2 : the characteristics of vihl level is basically the same as that of ttl level. but, its switching center point is a little higher than ttl s. refer to section recommended operating conditions . b0 b7 port p2 pull-up control register (address 0012 16 ) pup2 b0 b7 port p2 0 pull-up control bit 0: disabled 1: enabled port p2 1 pull-up control bit 0: disabled 1: enabled port p2 2 pull-up control bit 0: disabled 1: enabled port p2 3 pull-up control bit 0: disabled 1: enabled port p2 4 pull-up control bit 0: disabled 1: enabled port p2 5 pull-up control bit 0: disabled 1: enabled port p2 6 pull-up control bit 0: disabled 1: enabled port p2 7 pull-up control bit 0: disabled 1: enabled
7641 group rev.4.00 aug 28, 2006 page 15 of 135 rej03b0191-0400 table 6 list of i/o port function name port p0 port p1 port p2 input/output input/output, individual bits i/o format cmos input level cmos 3-state output non-port function lower address output higher address output data bus i/o related sfrs cpu mode register a port control register ref. no. (1) p0 0 /ab 0 C p0 7 /ab 7 p1 0 /ab 8 C p1 7 /ab 15 p2 0 /db 0 C p2 7 /db 7 p6 0 /dq 0 C p6 7 /dq 7 pin (2) cpu mode register a port control register port p2 pull-up control register cpu mode register a cpu mode register b port control register cpu mode register a cpu mode register b port control register timer x mode register timer y mode register interrupt polarity select register cpu mode register a port control register clock control register timer 123 mode register data bus buffer control register 0 port control register control signal i/o cmos input level/vihl input level cmos 3-state output port p3 (1) (3) (4) (5) cmos input level cmos 3-state output p3 0 /rdy C p3 7 /rd p4 0 /edma, port p4 p4 1 /int 0 , p4 2 /int 1 , p4 3 /cntr 0 , p4 4 /cntr 1 control signal i/o external interrupt p5 0 /x cin , p5 1 /t out / x cout cmos input level cmos 3-state output (6) (7) timer 1, timer 2 output pin sub-clock generat- ing input pin p5 2 /obf 0 , p5 3 /ibf 0 , p5 4 /s 0 , p5 5 /a 0 , p5 6 /r(e), p5 7 /w(r/w) port p5 cmos input level cmos 3-state output cmos input level/ttl input level in master cpu bus inferface function (8) (9) (10) cmos input level/ttl input level cmos 3-state output cmos input level cmos 3-state output cmos input level cmos 3-state output cmos input level/ttl input level in master cpu bus inferface function cmos input level cmos 3-state output (11) data bus buffer control register 0 port control register usb control register port control register data bus buffer control register 1 port control register cpu mode register b p7 0 /sof, port p6 port p7 p7 1 /hold, p7 2 /s 1 , p7 3 /ibf 1 / hlda, p7 4 /obf 1 (12) (13) (14) (15) (16) master cpu bus interface i/o pin master cpu bus interface i/o pin usb function output pin control signal i/o master cpu bus interface i/o pin (17) (18) (19) (20) (21) (22) (23) (24) uart1, 2 control registers serial i/o control register 1 serial i/o control register 2 port control register serial i/o i/o pin uart2 i/o pin uart1 i/o pin p8 0 /utxd 2 / srdy, p8 1 /urxd 2 / sclk, p8 2 /cts 2 / srxd, p8 3 /rts 2 / stxd, p8 4 /utxd 1 , p8 5 /urxd 1 , p8 6 /cts 1 , p8 7 /rts 1 port p8 notes 1 : for details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function i/o ports, refer to the applicable sections. 2 : make sure that the input level at each pin is either 0 v or v cc during execution of the stp instruction. when an input level is at an intermediate potential, a rush current will flow from v cc to v ss through the input-stage gate.
7641 group rev.4.00 aug 28, 2006 page 16 of 135 rej03b0191-0400 fig. 12 port block diagram (1) ( 1 ) p o r t s p 0 , p 1 , p 3 d a t a b u s d i r e c t i o n r e g i s t e r port latch ( 3 ) p o r t p 4 0 d a t a b u s di rect i on register port latch expanded data memory access bit e d m a s i g n a l (5) ports p4 3 , p4 4 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h t i m e r c o u n t e n a b l e d pulse output mode selected timers x, y output c n t r 0 , c n t r 1 i n p u t ( 2 ) p o r t p 2 data bus di rect i on register port latch p 2 p u l l - u p key interrupt input ( 4 ) p o r t s p 4 1 , p 4 2 d a t a b u s di rect i on register port latch s u b - c l o c k ( x c i n - x c o u t ) s t o p b i t int 0 , int 1 interrupt input (6) port p5 0 d a t a b u s di rect i on register port latch x c i n i n p u t
7641 group rev.4.00 aug 28, 2006 page 17 of 135 rej03b0191-0400 fig. 13 port block diagram (2) s 0 s 1 a 0 a 1 s0 s1 s 1 s 0 sof signal (7) port p5 1 data bus direction register port latch t out output control bit timer 1, 2 output ibf 0 output enable bit data bus direction register port latch ibf 0 output (9) port p5 3 (11) port p6 write to master cpu bus interface read from master cpu bus interface data bus direction register port latch dbbout 0 dbbs 0 dbbout 1 dbbs 1 dbbin 0 dbbin 1 (8) port p5 2 data bus direction register port latch obf 0 output (10) ports p5 4 to p5 7 data bus direction register port latch master cpu bus interface enable bit master cpu bus functions input ? (12) port p7 0 data bus direction register port latch usb sof port select bit ? : ports p5 4 to p5 7 functions pin name p5 4 p5 5 p5 6 p5 7 functions s 0 a 0 r(e) w(r/w) read from master cpu bus interface write to master cpu bus interface obf 0 output enable bit x cout output x cout oscillation drive disable bit sub-clock (x cin -x cout ) stop bit
7641 group rev.4.00 aug 28, 2006 page 18 of 135 rej03b0191-0400 fig. 14 port block diagram (3) h o l d s 1 h l d a ( 1 3 ) p o r t p 7 1 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h h o l d f u n c t i o n e n a b l e b i t h o l d f u n c t i o n e n a b l e b i t ( 1 5 ) p o r t p 7 3 i b f 1 o u t p u t e n a b l e b i t data bus buffer function select bit h o l d f u n c t i o n e n a b l e b i t di rect i on register p o r t l a t c h i b f 1 o u t p u t data bus (17) port p8 0 d i r e c t i o n r e g i s t e r p o r t l a t c h data bus s r d y o u t p u t s e l e c t b i t ( u a r t 2 ) t r a n s m i t e n a b l e b i t s r d y o u t p u t s p i m o d e s e l e c t b i t spi mode select bit c o n t r o l f o r s p i c o m p a t i b l e m o d e ( u a r t 2 ) u t x d 2 o u t p u t data bus buffer function select bit ( 1 4 ) p o r t p 7 2 data bus d i r e c t i o n r e g i s t e r p o r t l a t c h data bus buffer function select bit d a t a b u s b u f f e r f u n c t i o n s e l e c t b i t ( 1 6 ) p o r t p 7 4 data bus d i r e c t i o n r e g i s t e r port latch o b f 1 o u t p u t e n a b l e b i t o b f 1 o u t p u t (18) port p8 1 data bus di rect i on register port latch (serial i/o) internal synchronous clock select bits serial i/o port select bit (uart2) receive enable bit ( u a r t 2 ) r e c e i v e e n a b l e b i t (serial i/o) internal synchronous clock select bits (uart2) receive enable bit (uart2) urxd2 input serial i/o clock input serial i/o clock output
7641 group rev.4.00 aug 28, 2006 page 19 of 135 rej03b0191-0400 fig. 15 port block diagram (4) ( 1 9 ) p o r t p 8 2 d a t a b u s d i r e c t i o n r e g i s t e r p o r t l a t c h ( s e r i a l i / o ) s r x d i n p u t e n a b l e b i t ( u a r t 2 ) c t s f u n c t i o n e n a b l e b i t p o r t l a t c h ( u a r t 2 ) c t s f u n c t i o n e n a b l e b i t (uart2) cts 2 input ( s e r i a l i / o ) s r x d i n p u t ( 2 1 ) p o r t p 8 4 d a t a b u s p o r t l a t c h di rect i on register ( u a r t 1 ) t r a n s m i t e n a b l e b i t ( u a r t 1 ) u t x d 1 o u t p u t ( 2 3 ) p o r t p 8 6 d a t a b u s di rect i on register ( u a r t 1 ) c t s f u n c t i o n e n a b l e b i t p o r t l a t c h ( u a r t 1 ) c t s 1 i n p u t ( 2 0 ) p o r t p 8 3 d a t a b u s d i r e c t i o n r e g i s t e r ( u a r t 2 ) r t s f u n c t i o n e n a b l e b i t p o r t l a t c h transmit completed signal serial i/o port select bit s t x d o u t p u t c h a n n e l c o n t r o l b i t ( s e r i a l i / o ) s t x d o u t p u t ( u a r t 2 ) r t s 2 i n p u t ( 2 2 ) p o r t p 8 5 data bus di rect i on register port latch (uart1) receive enable bit (uart1) urxd1 input ( 2 4 ) p o r t p 8 7 d a t a b u s di rect i on register (uart1) rts function enable bit port latch ( u a r t 1 ) r t s 1 o u t p u t
7641 group rev.4.00 aug 28, 2006 page 20 of 135 rej03b0191-0400 interrupts there are twenty-four interrupt sources: five externals, eighteen internals, and one software. interrupt control each interrupt except the brk instruction interrupt has both an inter- rupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag (i). an interrupt occurs if the corresponding interrupt request and enable bits are 1 and the interrupt disable flag is 0 . interrupt enable bits can be set or cleared by software. interrupt re- quest bits can be cleared by software, but cannot be set by software. additionally, an active edge of int 1 and int 2 can be selected by using the interrupt edge select register (address 0011 16 ); an active edge of cntr 0 can be done by using the timer x mode register (address 0027 16 ); an active edge of cntr 1 can be done by using the timer y mode register (address 0028 16 ). the brk instruction interrupt and reset cannot be disabled with any flag or bit. the i flag disables all interrupts except the brk instruc- tion interrupt and reset. if several interrupts requests occur at the same time, the interrupt with the highest priority is accepted first. interrupt operation when an interrupt request occurs, the following operations are auto- matically performed: 1. the processing being executed is stopped. 2. the contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. the interrupt disable flag is set and the corresponding in- terrupt request bit is cleared. 4. the interrupt jump destination address is read from the vector table into the program counter. when setting the followings, the interrupt request bit may be set to 1 . ? when setting external interrupt active edge related register: interrupt polarity select register (address 0011 16 ) timer x mode register (address 0027 16 ) timer y mode register (address 0028 16 ) when not requiring for the interrupt occurrence synchronized with these setting, take the following sequence. ? set the corresponding interrupt enable bit to 0 (disabled). ? set the interrupt edge select bit (active edge switch bit). ? set the corresponding interrupt request bit to 0 after 1 or more instructions have been executed. ? set the corresponding interrupt enable bit to 1 (enabled). fig. 16 interrupt control i n t e r r u p t r e q u e s t b i t i n t e r r u p t e n a b l e b i t i n t e r r u p t d i s a b l e f l a g ( i ) brk instruction rese t interrupt request
7641 group rev.4.00 aug 28, 2006 page 21 of 135 rej03b0191-0400 interrupt source reset (note 3) usb function usb sof int 0 int 1 dmac0 dmac1 uart1 receive buffer full uart1 transmit uart1 summing error uart2 receive buffer full uart2 transmit uart2 summing error timer x timer y timer 1 timer 2 timer 3 cntr 0 cntr 1 serial i/o input buffer full output buffer empty key input (key- on wake-up) brk instruction priority 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 vector addresses (note 1) high fffb 16 fff9 16 fff7 16 fff5 16 fff3 16 fff1 16 ffef 16 ffed 16 ffeb 16 ffe9 16 ffe7 16 ffe5 16 ffe3 16 ffe1 16 ffdf 16 ffdd 16 ffdb 16 ffd9 16 ffd7 16 ffd5 16 ffd3 16 ffd1 16 ffcf 16 ffcd 16 ffcb 16 interrupt request generating conditions at reset ( note 2 ) at reception of sof packet at detection of either rising or falling edge of int 0 intput at detection of either rising or falling edge of int 1 input at completion of dmac0 transfer at completion of dmac1 transfer at completion of uart1 reception at completion of uart1 transmission at detection of uart1 summing error at completion of uart2 reception at completion of uart2 transmission at detection of uart2 summing error at timer x underflow at timer y underflow at timer 1 underflow at timer 2 underflow at timer 3 underflow at detection of either rising or falling edge of cntr 0 input at detection of either rising or falling edge of cntr 1 input at completion of serial i/o transmission/re- ception at writing to input data bus buffer at reading from output data bus buffer at falling of port p2 input logical level and at brk instruction execution remarks non-maskable external interrupt (active edge selectable) external interrupt (active edge selectable) low fffa 16 fff8 16 fff6 16 fff4 16 fff2 16 fff0 16 ffee 16 ffec 16 ffea 16 ffe8 16 ffe6 16 ffe4 16 ffe2 16 ffe0 16 ffde 16 ffdc 16 ffda 16 ffd8 16 ffd6 16 ffd4 16 ffd2 16 ffd0 16 ffce 16 ffcc 16 ffca 16 notes 1 : vector addresses contain interrupt jump destination addresses. 2 : usb function interrupt occurs owing to an interrupt request of the endpoint x (x = 0 to 4) in, endpoint x out, overrun/underru n, usb reset or suspend/ resume. 3 : reset functions in the same way as an interrupt with the highest priority. table 7 interrupt vector addresses and priority external interrupt (active edge selectable) external interrupt (active edge selectable) external interrupt (falling valid) non-maskable software interrupt
7641 group rev.4.00 aug 28, 2006 page 22 of 135 rej03b0191-0400 fig. 17 structure of interrupt-related registers i n t e r r u p t r e q u e s t r e g i s t e r a ( a d d r e s s 0 0 0 2 1 6 ) i r e q a u s b f u n c t i o n i n t e r r u p t r e q u e s t b i t u s b s o f i n t e r r u p t r e q u e s t b i t i n t 0 i n t e r r u p t r e q u e s t b i t i n t 1 i n t e r r u p t r e q u e s t b i t d m a c 0 i n t e r r u p t r e q u e s t b i t d m a c 1 i n t e r r u p t r e q u e s t b i t u a r t 1 r e c e i v e b u f f e r f u l l i n t e r r u p t r e q u e s t b i t u a r t 1 t r a n s m i t i n t e r r u p t r e q u e s t b i t b 7 b 0 i n t e r r u p t p o l a r i t y s e l e c t r e g i s t e r ( a d d r e s s 0 0 1 1 1 6 ) i p o l i n t 0 i n t e r r u p t e d g e s e l e c t b i t i n t 1 i n t e r r u p t e d g e s e l e c t b i t r e s e r v e d b i t s ( 0 a t r e a d / w r i t e ) 0 : f a l l i n g e d g e a c t i v e 1 : r i s i n g e d g e a c t i v e b 7 b 0 0 : i nterrupts di sa bl e d 1 : interrupts enabled 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d i nterrupt request reg i ster b a dd ress ( a dd ress 0003 16 ) ireqb uart 1 summ i ng error i nterrupt request bi t uart2 receive buffer full interrupt request bit uart2 transmit interrupt request bit uart2 summing error interrupt request bit timer x interrupt request bit timer y interrupt request bit timer 1 interrupt request bit timer 2 interrupt request bit b 7 b 0 0 : n o i nterrupt request i ssue d 1 : interrupt request issued i nterrupt contro l reg i ster a ( a dd ress 0005 16 ) icona usb f unct i on i nterrupt ena bl e bi t usb sof interrupt enable bit int 0 interrupt enable bit int 1 interrupt enable bit dmac0 interrupt enable bit dmac1 interrupt enable bit uart1 receive buffer full interrupt enable bit uart1 transmit interrupt enable bit b 7 b 0 i n t e r r u p t r e q u e s t r e g i s t e r c ( a d d r e s s 0 0 0 4 1 6 ) i r e q c t i m e r 3 i n t e r r u p t r e q u e s t b i t c n t r 0 i n t e r r u p t r e q u e s t b i t c n t r 1 i n t e r r u p t r e q u e s t b i t s e r i a l i / o i n t e r r u p t r e q u e s t b i t i n p u t b u f f e r f u l l i n t e r r u p t r e q u e s t b i t o u t p u t b u f f e r e m p t y i n t e r r u p t r e q u e s t b i t k e y i n p u t i n t e r r u p t r e q u e s t b i t r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) b 7 b 0 0 : n o i n t e r r u p t r e q u e s t i s s u e d 1 : i n t e r r u p t r e q u e s t i s s u e d i n t e r r u p t c o n t r o l r e g i s t e r b ( a d d r e s s 0 0 0 6 1 6 ) i c o n b uart 1 summ i ng error i nterrupt ena bl e bi t uart2 receive buffer full interrupt enable bit uart2 transmit interrupt enable bit uart2 summing error interrupt enable bit timer x interrupt enable bit timer y interrupt enable bit timer 1 interrupt enable bit timer 2 interrupt enable bit b 7 b 0 0 : i n t e r r u p t s d i s a b l e d 1 : i n t e r r u p t s e n a b l e d i nterrupt contro l reg i ster c ( a dd ress 0007 16 ) iconc ti mer 3 i nterrupt ena bl e bi t cntr 0 interrupt enable bit cntr 1 interrupt enable bit serial i/o interrupt enable bit input buffer full interrupt enable bit output buffer empty interrupt enable bit key input interrupt enable bit reserved bit ( 0 at read/write) b 7 b 0 0 : i nterrupts di sa bl e d 1 : interrupts enabled 0 000000 0
7641 group rev.4.00 aug 28, 2006 page 23 of 135 rej03b0191-0400 key input interrupt (key-on wake-up) a key input interrupt request is generated by applying l level to any pin of port p2 that have been set to input mode. in other words, it is generated when and of input level goes from 1 to 0 . an example of using a key input interrupt is shown in figure 18, where an inter- rupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports p2 0 C p2 4 . fig. 18 connection example when using key input interrupt and port p2 block diagram ?? ? p o r t p 2 7 l a t c h p o r t p 2 7 d i r e c t i o n r e g i s t e r = 1 p 2 7 o u t p u t p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 7 = 0 port pxx l level output k e y i n p u t i n t e r r u p t r e q u e s t f a l l i n g e d g e d e t e c t o r p2 6 output p 2 5 o u t p u t p2 4 input p 2 3 i n p u t p 2 2 i n p u t p 2 1 i n p u t p 2 0 i n p u t ?? ? p o r t p 2 6 l a t c h port p2 6 direction register = 1 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 6 = 0 f a l l i n g e d g e d e t e c t o r ??? p o r t p 2 5 l a t c h port p2 5 direction register = 1 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 5 = 0 f a l l i n g e d g e d e t e c t o r ??? p o r t p 2 4 l a t c h p o r t p 2 4 d i r e c t i o n r e g i s t e r = 0 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 4 = 0 f a l l i n g e d g e d e t e c t o r ?? ? p o r t p 2 3 l a t c h p o r t p 2 3 d i r e c t i o n r e g i s t e r = 0 port p2 pull-up control register bit 3 = 0 f a l l i n g e d g e d e t e c t o r ?? ? port p2 2 latch port p2 2 direction register = 0 port p2 pull-up control register bit 2 = 0 f a l l i n g e d g e d e t e c t o r ?? ? port p2 1 latch p o r t p 2 1 d i r e c t i o n r e g i s t e r = 0 p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 1 = 0 falling edge detector ?? ? p o r t p 2 0 l a t c h p o r t p 2 p u l l - u p c o n t r o l r e g i s t e r b i t 0 = 0 f a l l i n g e d g e d e t e c t o r p o r t p 2 0 d i r e c t i o n r e g i s t e r = 0 port p2 input reading circuit ? p-channel transistor for pull-up ?? cmos output buffer
7641 group rev.4.00 aug 28, 2006 page 24 of 135 rej03b0191-0400 timers the 7641 group has five timers: timer x, timer y, timer 1, timer 2, and timer 3. timer x and timer y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. all timers are down count timers. when the timer reaches 00 16 or 0000 16 , an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. when a timer underflows, the interrupt request bit corresponding to that timer is set to 1 . read and write operation on 16-bit timer must be performed for both high and low-order bytes. when reading a 16-bit timer, read the high-order byte first. when writing to a 16-bit timer, write the low-order byte first. the 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. fig. 19 timer block diagram p4 4 /cntr 1 p4 3 /cntr 0 q t scsgclk q t s p5 1 /t out /x cout timer x (low) (8) timer x (high) (8) timer x (low) latch (8) timer x (high) latch (8) / 8 / 16 / 32 / 64 timer x internal clock select bit timer x count source select bits timer x operating mode bits 00 01 timer x count stop bit 11 10 0 1 p5 4 direction register cntr 0 active edge switch bit cntr 0 active edge switch bit p4 3 latch pulse output mode pulse output mode q 0 1 falling edge detection rising edge detection pulse width hl continuously measurement mode pulse width hl continuously measurement, period measurement modes timer x interrupt request cntr 0 interrupt request timer x write control bit / 8 / 16 / 32 / 64 00 01 11 cntr 1 active edge switch bit 10 0 1 timer mode, ty out output enabled timer y operating mode bits timer y count stop bit timer y (low) (8) timer y (high) (8) timer y (low) latch (8) timer y (low) high (8) timer y write control bit q timer mode, ty out output enabled cntr 1 active edge switch bit 0 1 timer y operating mode bits 00 01 10 11 timer y interrupt request cntr 1 interrupt request timer 1 interrupt request timer 2 interrupt request timer 3 interrupt request timer 1 count source select bit 0 1 / 8 f(x cin ) / 2 timer 1 count stop bit timer 1 latch (8) timer 1 (8) timers 1, 2 write control bit timers 1, 2 write control bit 0 1 timer 2 count source select bit timer 2 latch (8) timer 2 (8) t out output control bit 0 1 t out output active edge switch bit t out output control bit t out source select bit q t q q t q q t q q t q t out output control bit 0 1 t out output active edge switch bit / 8 timer 3 count source select bit timer 3 latch (8) timer 3 (8) 0 1
7641 group rev.4.00 aug 28, 2006 page 25 of 135 rej03b0191-0400 fig. 20 structure of timer x mode register timer x timer x is a 16-bit timer that can be selected in one of four modes. the timer x s internal clock and count source can be selected and a write control is possible by using the timer x mode register. in all modes the count operation can halt by setting the timer x count stop bit to 1 . additionally, each timer underflow sets the interrupt request bit to 1 . (1) timer mode the timer counts the scsgclk (special count source genera- tor) or one of the internal clock divided by 8, 16, 32, 64. (2) pulse output mode each time the timer underflows, a signal output from the cntr 0 pin is inverted. except for this, the operation in pulse output mode is the same as in timer mode. when the cntr 0 active edge switch bit is 0 , the cntr 0 pin starts pulses output beginning at h ; when this bit is 1 , the cntr 0 pin starts pulses output beginning at l . when using a timer in this mode, set the port p4 3 direction regis- ter to output mode. (3) event counter mode the timer counts signals input through the cntr 0 pin. except for this, the operation in event counter mode is the same as in timer mode. when the cntr 0 active edge switch bit is 0 , the rising edge is counted; when this bit is 1 , the falling edge is counted. when using a timer in this mode, set the port p4 3 direction regis- ter to input mode. (4) pulse width measurement mode when the cntr 0 active edge switch bit is 0 , the timer counts while the input signal of cntr 0 pin is at h ; when it is 1 , the timer counts while the input signal of cntr 0 pin is at l . the timer counts the scsgclk or one of the internal clock di- vided by 8, 16, 32, 64 as its count source. when using a timer in this mode, set the port p4 3 direction regis- ter to input mode. if the timer x write control bit is 1 , when the value is written in the address of timer x, the value is loaded only in the latch. the value in the latch is loaded in timer x after timer x underflows. if the timer x write control bit is 0 , when the value is written in the address of timer x, the value is loaded in the timer x and the latch at the same time. when the value is to be written in latch only, unexpected value may be set in the high-order timer if the writing in high-order latch and the underflow of timer x are performed at the same timing. the cntr 0 interrupt active edge depends on the selection of cntr 0 active edge switch bit. t i m e r x m o d e r e g i s t e r ( a d d r e s s 0 0 2 7 1 6 ) t x m t i m e r x w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y t i m e r x c o u n t s o u r c e s e l e c t b i t s b 2 b 1 0 0 : / 8 0 1 : / 1 6 1 0 : / 3 2 1 1 : / 6 4 t i m e r x i n t e r n a l c l o c k s e l e c t b i t 0 : / n ( n = 8 , 1 6 , 3 2 , 6 4 ) 1 : s c s g c l k ( s p e c i a l c o u n t s o u r c e g e n e r a t o r ) t i m e r x o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : p u l s e o u t p u t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h m e a s u r e m e n t m o d e c n t r 0 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m h o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e h p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r i n t e r r u p t 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e s t a r t f r o m l o u t p u t i n p u l s e o u t p u t m o d e m e a s u r e l p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r i n t e r r u p t t i m e r x c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 0 b 7
7641 group rev.4.00 aug 28, 2006 page 26 of 135 rej03b0191-0400 timer y timer y is a 16-bit timer that can be selected in one of four modes. (1) timer mode the timer counts one of the internal clock divided by 8, 16, 32, 64. in the timer mode, a signal of which polarity is inverted each time the timer underflows is output from the cntr 1 pin. this is enabled by setting the timer y output control bit to 1 . when the cntr 1 active edge switch bit is 0 , the cntr 1 pin starts pulses output beginning at h ; when this bit is 1 , the cntr 1 pin starts pulses output beginning at l . when using a timer in this mode, set the port p4 4 direction regis- ter to output mode. (2) period measurement mode cntr 1 interrupt request is generated at a rising/falling edge of cntr 1 pin input signal. simultaneously, the value in timer y latch is reloaded in timer y and timer y continues counting down. ex- cept for the aforementioned operation, the operation in period measurement mode is the same as in timer mode. (the ty out output function is not usable.) the timer value just before the reloading at rising/falling of cntr 1 pin input signal is retained until the timer y is read once after the reload. the rising/falling timing of cntr 1 pin input signal is found by cntr 1 interrupt. when the cntr 1 active edge switch bit is 0 , the falling edge is detected; when this bit is 1 , the rising edge is detected. when using a timer in this mode, set the port p4 4 direction regis- ter to input mode. (3) event counter mode the timer counts signals input through the cntr 1 pin. except for this, the operation in event counter mode is the same as in timer mode. (the ty out output function is not usable.) when the cntr 1 active edge switch bit is 0 , the rising edge is counted; when this bit is 1 , the falling edge is counted. when using a timer in this mode, set the port p4 4 direction regis- ter to input mode. (4) pulse width hl continuously measurement mode cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal. except for this, the operation in pulse width hl continuously measurement mode is the same as in period measurement mode. when using a timer in this mode, set the port p4 4 direction regis- ter to input mode. fig. 21 structure of timer y mode register if the timer y write control bit is 1 , when the value is written in the address of timer y, the value is loaded only in the latch. the value in the latch is loaded in timer y after timer y underflows. if the timer y write control bit is 0 , when the value is written in the address of timer y, the value is loaded in the timer y and the latch at the same time. when the value is to be written in latch only, unexpected value may be set in the high-order timer if the writing in high-order latch and the underflow of timer y are performed at the same timing. the cntr 1 interrupt active edge depends on the selection of cntr 1 active edge switch bit. however, in pulse width hl continuously measurement mode, cntr 1 interrupt request is generated at both rising and falling edges of cntr 1 pin input signal regardless of the setting of cntr 1 active edge switch bit. t i m e r y m o d e r e g i s t e r ( a d d r e s s 0 0 2 8 1 6 ) t y m t i m e r y w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y t i m e r y o u t p u t c o n t r o l b i t 0 : t y o u t o u t p u t d i s a b l e d 1 : t y o u t o u t p u t e n a b l e d t i m e r y c o u n t s o u r c e s e l e c t b i t s b 3 b 2 0 0 : / 8 0 1 : / 1 6 1 0 : / 3 2 1 1 : / 6 4 t i m e r y o p e r a t i n g m o d e b i t s b 5 b 4 0 0 : t i m e r m o d e 0 1 : p e r i o d m e a s u r e m e n t m o d e 1 0 : e v e n t c o u n t e r m o d e 1 1 : p u l s e w i d t h h l c o n t i n u o u s l y m e a s u r e - m e n t m o d e c n t r 1 a c t i v e e d g e s w i t c h b i t 0 : c o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e f a l l i n g e d g e t o f a l l i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e f a l l i n g e d g e a c t i v e f o r i n t e r r u p t s t a r t f r o m h o u t p u t f o r t y o u t s i g n a l 1 : c o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e m e a s u r e t h e r i s i n g e d g e t o r i s i n g e d g e p e r i o d i n p e r i o d m e a s u r e m e n t m o d e r i s i n g e d g e a c t i v e f o r i n t e r r u p t s t a r t f r o m l o u t p u t f o r t y o u t s i g n a l t i m e r y c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p b 0 b 7
7641 group rev.4.00 aug 28, 2006 page 27 of 135 rej03b0191-0400 timer 1, timer 2, timer 3 timer 1, timer 2, and timer 3 are 8-bit timers. the count source for each timer can be selected by timer 123 mode register. when the timers 1, 2 write control bit is 1 and the values are written in the address of timers 1 and 2, the values are loaded only in their latches. the values in the latches are loaded in timers 1 and 2 after timers 1 and 2 underflow. when the timers 1, 2 write control bit is 0 and the values are written in the address of timers 1 and 2, the values are loaded in the timers 1 and 2 and their latches at the same time. a signal of which polarity is inverted each time the timer selected by the t out factor select bit underflows is output from the t out pin. this is enabled by setting the t out output control bit to 1 . when the t out output active edge switch bit is 0 , the t out pin starts pulses output beginning at h ; when this bit is 1 , the t out pin starts pulses output beginning at l . when using a timer in this mode, set the port p5 1 direction regis- ter to output mode. switching of the count sources of timers 1 to 3 does not affect the values of reload latches. however, that may make count operation started. therefore, write values again in the order of timers 1, 2 and then timer 3 after their count sources have been switched. when the value is to be written in latch only, unexpected value may be set in the timer if the writing in the latch and the timer un- derflow are performed at the same timing. fig. 22 structure of timer 123 mode register t i m e r 1 2 3 m o d e r e g i s t e r ( a d d r e s s 0 0 2 9 1 6 ) t 1 2 3 m t o u t f a c t o r s e l e c t b i t 0 : t i m e r 1 o u t p u t 1 : t i m e r 2 o u t p u t t i m e r 1 c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p t i m e r 1 c o u n t s o u r c e s e l e c t b i t 0 : / 8 1 : f ( x c i n ) / 2 t i m e r 2 c o u n t s o u r c e s e l e c t b i t 0 : t i m e r 1 o u t p u t 1 : t i m e r 3 c o u n t s o u r c e s e l e c t b i t 0 : t i m e r 1 o u t p u t 1 : / 8 t o u t o u t p u t a c t i v e e d g e s w i t c h b i t 0 : s t a r t a t h o u t p u t 1 : s t a r t a t l o u t p u t t o u t o u t p u t c o n t r o l b i t 0 : t o u t o u t p u t d i s a b l e d 1 : t o u t o u t p u t e n a b l e d ti m e r s 1 , 2 w r i t e c o n t r o l b i t 0 : w r i t e v a l u e i n l a t c h a n d c o u n t e r 1 : w r i t e v a l u e i n l a t c h o n l y b 0 b 7
7641 group rev.4.00 aug 28, 2006 page 28 of 135 rej03b0191-0400 serial interface serial i/o the serial i/o can be used only for clock synchronous serial i/o. the transmitter and the receiver must use the same clock. if the internal clock is used, transfer is started by a write signal to the serial i/o shift register. [serial i/o control register 1 (siocon1)] 002b 16 [serial i/o control register 2 (siocon2)] 002c 16 each of the serial i/o control registers 1 and 2 contains eight bits which control various serial i/o functions. fig. 23 structure of serial i/o control registers 1, 2 s e r i a l i / o c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 0 2 b 1 6 ) s i o c o n 1 i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s ( n o t e 1 ) b 2 b 1 b 0 0 0 0 : i n t e r n a l c l o c k d i v i d e d b y 2 0 0 1 : i n t e r n a l c l o c k d i v i d e d b y 4 0 1 0 : i n t e r n a l c l o c k d i v i d e d b y 8 0 1 1 : i n t e r n a l c l o c k d i v i d e d b y 1 6 1 0 0 : i n t e r n a l c l o c k d i v i d e d b y 3 2 1 0 1 : i n t e r n a l c l o c k d i v i d e d b y 6 4 1 1 0 : i n t e r n a l c l o c k d i v i d e d b y 1 2 8 1 1 1 : i n t e r n a l c l o c k d i v i d e d b y 2 5 6 s e r i a l i / o p o r t s e l e c t b i t 0 : i / o p o r t 1 : s t x d , s c l k s i g n a l o u t p u t s r d y o u t p u t s e l e c t b i t 0 : i / o p o r t 1 : s r d y s i g n a l o u t p u t t r a n s f e r d i r e c t i o n s e l e c t b i t 0 : l s b f i r s t 1 : m s b f i r s t s y n c h r o n o u s c l o c k s e l e c t b i t 0 : e x t e r n a l c l o c k 1 : i n t e r n a l c l o c k st x d o u t p u t c h a n n e l c o n t r o l b i t 0 : c m o s o u t p u t 1 : n - c h a n n e l o p e n d r a i n o u t p u t notes 1 : the source of serial i/o internal synchronous clock can be selected by bit 1 of serial i/o control register 2. 2 : to set the slave mode, also set bit 4 of serial i/o control register 1 to 1 . b 0 b 7 s e r i a l i / o c o n t r o l r e g i s t e r 2 ( a d d r e s s 0 0 2 c 1 6 ) s i o c o n 2 spi mode select bit 0: normal serial i/o mode 1: spi compatible mode ( note 2 ) serial i/o internal clock select bit 0: 1: scsgclk srxd input enable bit 0: srxd input disabed 1: srxd input enabed clock polarity select bit (cpol) 0: sclk starting at l 1: sclk starting at h clock phase select bit (cpha) 0: serial transfer starting at falling edge of srdy 1: serial transfer starting afer a half cycle of sclk passed at falling edge of srdy reserved bits ( 0 at read/write) b 0 b 7 000
7641 group rev.4.00 aug 28, 2006 page 29 of 135 rej03b0191-0400 fig. 24 block diagram of serial i/o 1/2 1/ 4 1/8 1/16 1/32 1/64 1/128 1/256 scsgclk p8 1 /urxd 2 /sclk p8 3 /rts 2 /stxd p 8 2 / c t s 2 / s r x d p 8 0 / u t x d 2 / s r d y d a t a b u s i n t e r n a l s y n c h r o n o u s c l o c k s e l e c t i o n b i t s serial i/o internal clock select bit 1 0 0 1 s e r i a l i / o i n t e r r u p t r e q u e s t s y n c h r o n i z a t i o n c i r c u i t s y n c h r o n o u s c l o c k s e l e c t b i t s r d y o u t p u t s e l e c t b i t e x t e r n a l c l o c k p8 0 latch 1 0 serial i/o counter (3) serial i/o shift register (8) spi mode select bit p8 1 latch 0 1 serial i/o port select bit p8 3 latch 0 1 serial i/o port select bit 1 0 s r x d i n p u t e n a b l e b i t d i v i d e r
7641 group rev.4.00 aug 28, 2006 page 30 of 135 rej03b0191-0400 the serial i/o counter is set to 7 by writing operation to the serial i/o shift register (address 002a 16 ). when the srdy output select bit is 1 , the srdy pin goes l after that writing. on the negative edge of the transfer clock the srdy pin returns h and the data of the first bit is transmitted from the stxd pin. the remaining data are done from the stxd pin bit by bit on each falling edge of the transfer clock. additionally, the data is latched from the srxd pin on each rising edge of the transfer clock and then the contents of the serial i/o shift register are shifted by one bit. when the internal system clock is selected as the transfer clock, the followings occur at counting eight transfer clocks: ? the serial i/o counter reaches 0 ? the transfer clock halts at h ? the serial i/o interrupt request bit is set to 1 ? the stxd pin goes a high-impedance state after an 8-bit transfer is completed. when the external clock is selected as the transfer clock, the fol- lowings occur at counting eight transfer clocks: ? the serial i/o counter reaches 0 ? the serial i/o interrupt request bit is set to 1 in this case, the transfer clock needs to be controlled by the exter- nal source because the transfer clock does not halt. additionally, the stxd pin does not go a high-impedance state after an 8-bit transfer is completed. figure 25 shows serial i/o timing. fig. 25 serial i/o timing d 1 d 0 d 2 d 3 d 4 d 5 d 6 d 7 first last stxd/srxd synchronizing clock sclk (cpol = 1, cpha =1 ) sclk (cpol = 0, cpha = 1) sclk (cpol = 1, cpha = 0) sclk (cpol = 0, cpha = 0) normal mode timing (lsb first) transfer clock synchronizing clock serial i/o shift register write signal srdy signal serial i/o output stxd serial i/o input srxd (note) interrupt request bit is set to 1 . note : when the internal clock is selected as the transfer clock, the stxd pin goes to a high-impedance state after transfer complet ion. spi compatible mode timing srdy signal
7641 group rev.4.00 aug 28, 2006 page 31 of 135 rej03b0191-0400 setting the spi mode select bit (bit 0 of siocon2) puts the serial i/o in spi compatible mode. the synchronous clock select bit (bit 6 of siocon1) determines whether the serial i/o is an spi master or slave. when the external clock is selected ( 0 ), the se- rial i/o is in slave mode; when the internal clock is selected ( 1 ), the serial i/o is in master mode. in spi compatible mode the srxd pin functions as a miso (mas- ter in/slave out) pin and the stxd pin functions as a mosi (master out/slave in) pin. in slave mode the transmit data is output from the miso pin and the receive data is input from the miso pin. the srdy pin func- tions as the chip-select signal input pin from an external. in master mode the transmit data is output from the mosi pin and the receive data is input from the miso pin. the srdy pin func- tions as the chip-select signal output pin to an external. ? slave mode operation in slave mode of spi compatible mode 4 types of clock polarity and clock phase can be usable by bits 3 and 4 of serial i/o control register 2. if the srdy pin is held h , the shift clock is inhibited, the serial i/ o counter is set to 7 . if the srdy pin is held l , then the shift clock will start. make sure during transfer to maintain the srdy input at l and not to write data to the serial i/o counter. figure 25 shows the serial i/o timing.
7641 group rev.4.00 aug 28, 2006 page 32 of 135 rej03b0191-0400 uart1, uart2 the uart consists of two channels: uart1 and uart2. each has a dedicated timer provided to generate transfer clocks and op- erates independently. both uart1 and uart2 have the same functions. twelve serial data transfer formats can be selected, and the trans- fer formats used by a transmitter and receiver must be identical. the transmit and receive shift registers each have a buffer, but the two buffers have the same address in a memory. since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. the transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. the transfer speed (baud rate) is expression as follows: transfer speed (baud rate) = fi / {(n + 1) ? 16 } n: the contents of uartx (x = 1, 2) baud rate generator fi: using uart clock prescaling select bits, select any one of , / 8, /32, /256, scsgclk, scsgclk/8, scsgclk/32 and scsgclk/256 o e r per fer 0034 16 003c 16 receive buffer register 1 receive buffer register 2 receive shift register 1 receive shift register 2 address 0030 16 address 0038 16 u a r t x m o d e r e g i s t e r uartx control register a d d r e s s 0 0 3 3 1 6 a d d r e s s 0 0 3 b 1 6 r e c e i v e b u f f e r f u l l f l a g ( r b f ) r e c e i v e b u f f e r f u l l i n t e r r u p t r e q u e s t ( u x r b f ) r e c e i v e s u m m i n g e r r o r i n t e r r u p t r e q u e s t ( u x e s ) spdetector uart character length select bits 7 bits 8 b i t s 9 bits s t d e t e c t o r p 8 5 / u r x d 1 p 8 1 / u r x d 2 / s c l k p 8 4 / u t x d 1 p 8 0 / u t x d 2 / s r d y s c s g c l k p r e s c a l e r 1 / 1 1/8 1/32 1 / 2 5 6 baud rate generator s t / s p / p a g e n e r a t o r clock control circuit 1 / 1 6 a d d r e s s e s 0 0 3 5 1 6 a d d r e s s e s 0 0 3 d 1 6 p 8 6 / c t s 1 p 8 2 / c t s 2 / s r x d rts control register p8 7 /rts 1 p8 3 /rts 2 /stxd frequency division ratio 1/(n+1) a d d r e s s e s 0 0 3 6 1 6 a d d r e s s e s 0 0 3 e 1 6 a d d r e s s e s 0 0 3 1 1 6 a d d r e s s e s 0 0 3 9 1 6 character length select bit t r a n s m i t s h i f t r e g i s t e r 1 t r a n s m i t s h i f t r e g i s t e r 2 t r a n s m i t b u f f e r r e g i s t e r 1 t r a n s m i t b u f f e r r e g i s t e r 2 t r a n s m i t c o m p l e f l a g ( t c m ) transmit interrupt source select bit transmit interrupt request (uxtx) t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) uart status register data bus data bus uart clock prescaling select bits u a r t c l o c k s e l e c t b i t 0034 16 003c 16 a d d r e s s e s 0 0 3 5 1 6 a d d r e s s e s 0 0 3 d 1 6 address 0032 16 address 003a 16 fig. 26 uartx (x = 1, 2) block diagram
7641 group rev.4.00 aug 28, 2006 page 33 of 135 rej03b0191-0400 as a transmitter, the uart can be configured to recognize the clear-to-send (ctsx) input as a handshaking signal. this is en- abled by setting the cts function enable bit (bit 5 of uxcon) to 1 . if cts function is enabled, even when transmission is enabled and the uartx transmit buffer register is filled with the data, the transmission never starts; but it will start when inputting l to the ctsx pin. figures 27 and 28 show the uartx transmit timings. u t x d o u t p u t ( p 8 4 / u t x d 1 , p 8 0 / u t x d 2 / s r d y ) d 0 d 1 sp s t d 2 d 3 d 4 d 5 d 6 d 7 p st s p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 p c t s x p i n ( p 8 6 / c t s 1 , p 8 2 / c t s 2 / s r x d ) t r a n s f e r c l o c k t r a n m i t e n a b l e b i t t r a n s m i t b u f f e r e m p t y f l a g t r a n s m i t c o m p l e t e f l a g data set into uartx transmit buffer register 1 data transferring from uartx transmit buffer register 1 to transmit shift register 1 halt due to cts = h halt due to tranmit enable bit = 0 t h i s t i m i n g a p p l y i n g t o t h e c o n d i t i o n s : ? c h a r a c t e r l e n g t h = 8 b i t s ? p a r i t y e n a b l e d ? 1 s t o p b i t reception is enabled when the receive enable bit is 1 . detec- tion of the start bit makes transfer clocks generated and the data reception starts in the lsb first. when using 9-bit character length, read the received data from the uartx receive buffer register 2 (high-order byte) first before the uartx receive buffer register 1 (low-order byte). reception requires the following setup: (1) define a baud rate by setting a value n (n = 0 to 255) into uartx baud rate generator (addresses 0031 16 , 0039 16 ). (2) set the receive initialization bit (bit 3 of uxcon) to 1 . (3) configure the data format and clock selection by setting the uartx mode register. (4) set the rts function enable bit (bit 5 of uxcon) if rts func- tion will be used. (5) set the receive enable bit (bit 1 of uxcon) to 1 . fig. 27 uartx transmit timing (cts function enabled) transmission starts when the transmit enable bit is 1 and the transmit buffer empty flag is 0 . additionally, when cts function enabled, the ctsx pin must be l to be started. the data in which start bit and stop bit or parity bit are also added is transmitted from the low-order byte sequentially. when using 9-bit character length, set the data into the uartx transmit buffer register 2 (high-order byte) first before the uartx transmit buffer register 1 (low-order byte). once the transmission starts, the transmit enable bit, the trans- mit buffer empty flag and the ctsx pin state (when this is enabled) could not be checked until the transmission in progress has ended. transmission requires the following setup: (1) define a baud rate by setting a value n (n = 0 to 255) into uartx baud rate generator (addresses 0031 16 , 0039 16 ). (2) set the transmit initialization bit (bit 2 of uxcon) to 1 . this will set the uartx status register to 03 16 . (3) select the interrupt source with the transmit interrupt source select bit (bit 4 of uxcon). (4) configure the data format and clock selection by setting the uartx mode register. (5) set the cts function enable bit (bit 5 of uxcon) if cts func- tion will be used. (6) set the transmit enable bit (bit 0 of uxcon) to 1 . if updating a value of uartx baud rate generator while the data is being transmitted, be sure to disable the transmission before up- dating. if the former data remains in the uartx transmit buffer registers 1 and 2 at retransmission, an undefined data might be output.
7641 group rev.4.00 aug 28, 2006 page 34 of 135 rej03b0191-0400 utxd output (p8 4 /utxd 1 , p8 0 /utxd 2 /srdy) d 0 d 1 sp st d 2 d 3 d 4 d 5 d 6 d 7 p sp t r a n s f e r c l o c k t r a n m i t e n a b l e b i t t r a n s m i t b u f f e r e m p t y f l a g t r a n s m i t c o m p l e t e f l a g d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 st d a t a s e t i n t o u a r t x t r a n s m i t b u f f e r r e g i s t e r 1 data transferring from uartx transmit buffer register 1 to transmit shift register 1 this timing applies to the conditions: ? character length = 8 bits ? parity enabled ? 1 stop bit as a receiver, the uart can be configured to generate the re- quest-to-send (rtsx) handshaking signal. this is enabled by setting the rts function enable bit (bit 6 of uxcon) to 1 . when reception is enabled, that is the receive enable bit is 1 , the rtsx pin goes l to inform a transmitter that reception is pos- sible. the rtsx pin goes h at reception starting and does l at receiving of the last bit. the delay time from the reception of the last stop bit to the asser- tion of rtsx is selectable using the rts assertion delay count select bits. brgx (x = 1, 2) count source d 0 urxd (p8 5 /urxd 1 , p8 1 /urxd 2 /sclk) st sp d 1 d 7 rtsx pin (p8 7 /rts 1 , p8 3 /rts 2 /stxd) receive enable bit receive buffer empty flag transfer clock transfer clock generated at falling edge of start bit and receive started receive data latched data transferring from uartx receive register 1 to receive buffer register 1 ( note ) note: when no rts assertion delay, the rtsx pin goes l . the rts assertion delay counts are selected by bits 4 to 7 of uartx rts control register. this timing applies to the conditions: ? character length = 8 bits ? parity enabled ? 1 stop bit fig. 28 uartx transmit timing (cts function disbled) when the receive enable bit is set to 0 or the receive initializa- tion bit is set to 1 , the rtsx pin goes h . even when the receive enable bit is set to 1 , the rtsx pin goes h if detecting an invalid start bit. figure 29 shows the uartx receive timing. fig. 29 uartx transmit timing (rts function enabled)
7641 group rev.4.00 aug 28, 2006 page 35 of 135 rej03b0191-0400 the uart address mode is intended for use to communicate be- tween the specified mcus in a multi-mcu environment. the uart address mode can be used in either an 8-bit or 9-bit char- acter length. an address is identified by the msb of the incoming data being 1 . the bit is 0 for non-address data. when the msb of the incoming data is 0 in the uart address mode, the receive buffer full flag is set to 1 , but the receive buffer full interrupt request bit is not set to 1 . when the msb of the incoming data is 1 , normal receive operation is performed. in the uart address mode an overrun error is not detected for re- ception of the 2nd and onward bytes. an occurrence of framing error or parity error sets the summing error interrupt request bit to 1 and the data is not received independent of its msb con- tents. usage of uart address mode is explained as follows: (1) set the uart address mode enable bit to 1 . (2) sends the address data of a slave mcu first from a host mcu to all slave mcus. the msb of address data must be 1 and the remaining 7 bits specify the address. (3) the all slave mcus automatically check for the received data whether its stop bit is valid or not, and whether the parity error occurs or not (when the parity enabled). if these errors occur, the framing error flag or parity error flag and the summing error flag are set to 1 . then, the summing error interrupt request bit is also set to 1 . (4) when received data has no error, the all slave mcus must judge whether the address of the received address data matches with their own addresses by a program. after the msb being 1 is received, the uart address mode enable bit is automatically set to 0 (disabled). (5) the uart address mode enable bit of the slave mcus which have be judged that the address does not match with them must be set to 1 (enabled) again by a program to disable re- ception of the following data. (6) transmit the data of which msb is 0 from the host mcu. the slave mcus disabling the uart address mode receive the data, and their receive buffer full flags and the receive buffer full interrupt request bits are set to 1 . for the other slave mcus enabling the uart address mode, their receive buffer full flag are set to 1 , but their receive buffer full in- terrupt request bits are not set to 1 . (7) an overrun error cannot be detected after the first data has been received in uart address mode. accordingly, even if the slave mcus does not read the received data and the next data has been received, an overrun error does not occur. thus, a communication between a host mcu and the specified mcu can be realized. [uartx (x = 1, 2) mode register (uxmod)] 0030 16 , 0038 16 the uart x mode register consists of 8 bits which set a transfer data format and an used clock. [uartx (x = 1, 2) baud rate generator (uxbrg)] 0031 16 , 0039 16 the uartx baud rate generator determines the baud rate for transfer. the baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. the reset cannot affect the contents of baud rate generator. [uartx (x = 1, 2) status register (uxsts)] 0032 16 , 003a 16 the read-only uartx status register consists of seven flags (bits 0 to 6) which indicate the uart operating status and various er- rors. when the uart address mode is enabled , the setting and clear- ing conditions of each flag differ from the following explanations. these differences are explained in section uart address mode . ? transmit complete flag (tcm) in the case where no data is contained in the transmit buffer reg- ister, the transmit complete flag (tcm) is set to 1 when the last bit in the transmit shift register is transmitted. the tcm flag is also set to 1 at reset or initialization by setting the transmit initialization bit (bit 2 of uxcon). it is set to 0 when transmission starts, and it is kept during the transmission. ? transmit buffer empty flag (tbe) the transmit buffer empty flag (tbe) is set to 1 when the con- tents of the transmit buffer register are loaded into the transmit shift register. the tbe flag is also set 1 at the hardware reset or initialization by setting the transmit initialization bit. it is set to 0 when a write operation is performed to the low-order byte of the transmit buffer register. ? receive buffer full flag (rbf) the receive buffer full flag (rbf) is set to 1 when the last stop bit of the data is received. the rbf flag is set to 0 when the low- order byte of the receive buffer register is read, at the hardware reset or initialization by setting the transmit initialization bit.
7641 group rev.4.00 aug 28, 2006 page 36 of 135 rej03b0191-0400 if there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set to 1 . the all error flags per, fer, oer and ser are cleared to 0 when the uartx status register is read, at the hardware reset or initializa- tion by setting the transmit initialization bit. the summing error flag (ser) is set to 1 when any one of the per, fer and oer is set to 1 . the parity error flag (per) is set to 1 when the sum total of 1s of received data and the parity does not correspond with the se- lection with the parity select bit (pmd). it is enabled only if the parity enable bit (bit 5 of uxmod) is set to 1 . the framing error flag (fer) is set to 1 when the number of stop bit of the received data does not correspond with the selec- tion with the stop bit length select bit (stb). the overrun flag flag (oer) is set to 1 if the previous data in the low-order byte of the receive buffer register 1 (addresses 0034 16 , 003c 16 ) is not read before the current receive operation is completed. it is also set 1 if any one of error flags is 1 for the previous data and the current receive operation is completed. be sure to read uartx status register to clear the error flags before the next reception has been completed. [uartx (x = 1, 2) control register (uxcon)] 0033 16 , 003b 16 the uartx control register consists of eight control bits for the uartx function. this register can enable the cts, rts and uart address mode. if the transmit enable bit (ten) is set to 0 (disabled) while a data is being transmitted, the transmitting operation will stop after the data has been transmitted. if the receive enable bit (ren) is set to 0 (diabled) while a data is being received, the receiving operation will stop after the data has been received. when setting the transmit initialization bit (tin) to 1 , the ten bit is set to 0 and the uartx status register will be set to 03 16 af- ter the data has been transmitted. to retransmit, set the ten to 1 and set a data to the transmit buffer register again. the tin bit will be cleared to 0 one cycle later after the tin bit has been set to 1 . setting the receive initialization bit (rin) to 1 sets all of the ren, rbf and the receive error flags (per, fer, oer, ser) to 0 . the rin bit will be cleared to 0 one cycle later after the rin bit has been set to 1 . when cts or rts function is disabled, pins cts 1 and cts 2 or rts 1 and rts 2 can be used as ordinary i/o ports, correspond- ingly. [uartx transmit/receive buffer registers 1, 2 (uxtrb1/ uxtrb2)] 0034 16 , 0035 16 , 003c 16 , 003d 16 the transmit buffer register and the receive buffer register are lo- cated at the same address. the transmit buffer register is write-only and the receive buffer register is read-only. if a charac- ter bit length is 7 bits, the msb of received data is invalid. if a character bit length is 7 or 8 bits, the received contents of uxtrb2 are also invalid. if a character bit length is 9 bits, the received high-order 7 bits of uxtrb2 are 0 . [uartx (x = 1, 2) rts control register (uxrts)] 0036 16 , 003e 16 the delay time from the reception of the last stop bit to the asser- tion of rtsx is selectable using the rts assertion delay count select bits. if the stop bit is detected before rts assertion delay time has expired, the rtsx pin is kept h . the rts assertion de- lay count starts after the last data reception is completed. setting the rin bit to 1 resets the uxrts. after setting the rin bit to 1 , set this uxrts.
7641 group rev.4.00 aug 28, 2006 page 37 of 135 rej03b0191-0400 fig. 30 structure of uart related registers u a r t x m o d e r e g i s t e r ( a d d r e s s e s 0 0 3 0 1 6 , 0 0 3 8 1 6 ) u x m o d u a r t c l o c k s e l e c t b i t ( c l k ) 0 : 1 : s c s g c l k u a r t c l o c k p r e s c a l i n g s e l e c t b i t s ( p s ) b 2 b 1 0 0 : u a r t c l o c k d i v i d e d b y 1 0 1 : u a r t c l o c k d i v i d e d b y 8 1 0 : u a r t c l o c k d i v i d e d b y 3 2 1 1 : u a r t c l o c k d i v i d e d b y 2 5 6 s t o p b i t l e n g t h s e l e c t b i t ( s t b ) 0 : 1 s t o p b i t 1 : 2 s t o p b i t s p a r i t y s e l e c t b i t ( p m d ) 0 : e v e n p a r i t y 1 : o d d p a r i t y p a r i t y e n a b l e b i t ( p e n ) 0 : p a r i t y c h e c k i n g d i s a b l e d 1 : p a r i t y c h e c k i n g e n a b l e d u a r t ch a r a c t e r l e n g t h s e l e c t b i t b 7 b 6 0 0 : 7 b i t s 0 1 : 8 b i t s 1 0 : 9 b i t s 1 1 : n o t a v a i l a b l e b 0 b 7 u a r t x c o n t r o l r e g i s t e r ( a d d r e s s e s 0 0 3 3 1 6 , 0 0 3 b 1 6 ) u x c o n transmit enable bit (ten) 0: transmit disabled 1: transmit enabled receive enable bit (ren) 0: receive disabled 1: receive enabled transmit initialization bit (tin) 0: no action. 1: initializing receive initialization bit (rin) 0: no action. 1: initializing transmit interrupt source select bit (tis) 0: interrupt when transmit buffer has emptied 1: interrupt when transmit shift operation is completed cts function enable bit (cts_sel) 0: cts function disabled 1: cts function enabled rts function enable bit (rts_sel) 0: rts function disabled 1: rts function enabled uart address mode enable bit (ame) 0: address mode disabled 1: address mode enabled b 0 b 7 u a r t x s t a t u s r e g i s t e r ( a d d r e s s e s 0 0 3 2 1 6 , 0 0 3 a 1 6 ) u x s t s t r a n s m i t c o m p l e t e f l a g ( t c m ) 0 : t r a n s m i t s h i f t i n p r o g r e s s 1 : t r a n s m i t s h i f t c o m p l e t e d t r a n s m i t b u f f e r e m p t y f l a g ( t b e ) 0 : b u f f e r f u l l 1 : b u f f e r e m p t y r e c e i v e b u f f e r f u l l f l a g ( r b f ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l p a r i t y e r r o r f l a g ( p e r ) 0 : n o e r r o r 1 : p a r i t y e r r o r f r a m i n g e r r o r f l a g ( f e r ) 0 : n o e r r o r 1 : f r a m i n g e r r o r o v e r r u n e r r o r f l a g ( o e r ) 0 : n o e r r o r 1 : o v e r r u n e r r o r s u m m i n g e r r o r f l a g ( s e r ) 0 : ( f e r ) u ( o e r ) u ( s e r ) = 0 1 : ( f e r ) u ( o e r ) u ( s e r ) = 1 r e s e r v e d b i t s ( 0 a t r e a d / w r i t e ) b0 b7 u a r t x r t s c o n t r o l r e g i s t e r ( a d d r e s s e s 0 0 3 6 1 6 , 0 0 3 e 1 6 ) u x r t s c reserved bits ( 0 at read/write) rts assertion delay count select bits b7 b6 b5 b4 0 0 0 0 : no delay; assertion immediately 0 0 0 1 : 8-bit term assertion at h 0 0 1 0 : 16-bit term assertion at h 0 0 1 1 : 24-bit term assertion at h 0 1 0 0 : 32-bit term assertion at h 0 1 0 1 : 40-bit term assertion at h 0 1 1 0 : 48-bit term assertion at h 0 1 1 1 : 56-bit term assertion at h 1 0 0 0 : 64-bit term assertion at h 1 0 0 1 : 72-bit term assertion at h 1 0 1 0 : 80-bit term assertion at h 1 0 1 1 : 88-bit term assertion at h 1 1 0 0 : 96-bit term assertion at h 1 1 0 1 : 104-bit term assertion at h 1 1 1 0 : 112-bit term assertion at h 1 1 1 1 : 120-bit term assertion at h b0 b7 0 0 0 0
7641 group rev.4.00 aug 28, 2006 page 38 of 135 rej03b0191-0400 fig. 31 dmacx (x = 0, 1) block diagram dmac the 7641 group is equipped with 2 channels of dmac (direct memory access controller) which enable high speed data transfer from a memory to a memory without use of the cpu. the dmac initiates the data transfer with an interrupt factor speci- fied by the dmac channel x (x = 0, 1) hardware transfer request source bit (dxhr), or with a software trigger. the dxtms [dma channel x (x = 0, 1) transfer mode selection bit] selects one of two transfer modes; cycle steal mode or burst transfer mode. in the cycle steal mode, the dmac transfers one byte of data for each request. in the burst transfer mode, the dmac transfers the number of bytes data specified by the transfer count register for each request. the count register is a 16-bit counter; the maximum number of data is 65,536 bytes per one re- quest. figure 31 shows the dma control block diagram and figure 32 shows the structure of dmac related registers. [dmac index and status register] dmais the dmac index and status register consists of various control bits for the dmac and its status flags. the dma channel index bit (dci) selects which channel ( 0 or 1) will be accessed, since the mode registers, source registers, des- tination registers and transfer count register of both dmac channels share the same sfr addresses, respectively. [dmac channel x (x = 0, 1) mode registers 1, 2] dmaxm1, dmaxm2 the 16 bits of dmac channel x mode registers 1 and 2 control each operation of dmac channels 0 and 1. when the dmac channel x (x = 0, 1) write bit (dxdwc) is 0, data is simultaneously written into each latch and register of the source registers, destination register, and transfer count reg- isters. when this bit is 1, data is written only into their latches. when data is read from each register, it must be read from the higher bytes first, then the lower bytes. when writing data, write to the lower bytes first, then the higher bytes. i n t e r r u p t : u a r t 1 r e c e i v e , u a r t 1 t r a n s m i t , s e r i a l i / o , i n t 0 , t i m e r y , c n t r 1 s i g n a l : o b e 0 , i b f 0 ( d a t a ) , e p ( e n d p o i n t ) 1 r e c e i v e / t r a n s m i t e p ( e n d p o i n t ) 2 r e c e i v e / t r a n s m i t e p ( e n d p o i n t ) 3 r e c e i v e / t r a n s m i t e p 1 o u t f i f o d a t a e x i s t i n g interrupt : uart2 receive, uart2 transmit, int 1 , timer 1, timer x, cntr 0 signal : obe 1 , ibf 1 (data), ep (endpoint) 1 receive/transmit ep (endpoint) 2 receive/transmit ep (endpoint) 4 receive/transmit ep1out fifo data existing c a s e o f d m a c c h a n n e l 0 case of dmac channel 1 dmac channel x channel x timing generator channel x transfer source register ch a n n e l x t r a n s f e r d e s t i n a t i o n r e g i s t e r channel x transfer count register i n t e r r u p t g e n e r a t o r d m a c x i n t e r r u p t r e q u e s t a d d r e s s b u s dxcen dxcrr dxumie dxswt dxhrs3 dxhrs2 dxhrs1 dxhrs0 dxsrce dxsrid dxrld drldd d x d r c e d x d r i d d x r l d d r l d d i n t e r r u p t d i s a b l e f l a g ( i f l a g ) temporary register index status register d x u f dxdaue mode 1 register d x t m sdtsc m o d e 2 r e g i s t e r channel x transfer source latch c h a n n e l x t r a n s f e r d e s t i n a t i o n l a t c h channel x transfer count latch dxdwc dxdwc dxdwc d a t a b u s d a t a b u s d x u f d x s f i 15 0 1 5015 0
7641 group rev.4.00 aug 28, 2006 page 39 of 135 rej03b0191-0400 d m a c in d e x a n d s t a t u s r e g i s t e r ( a d d r e s s 0 0 3 f 1 6 ) d m a i s d m a c c h a n n e l 0 c o u n t r e g i s t e r u n d e r f l o w f l a g ( d 0 u f ) 0 : n o u n d e r f l o w 1 : u n d e r f l o w g e n e r a t e d d m a c c h a n n e l 0 s u s p e n d f l a g ( d 0 s f i ) 0 : n o t s u s p e n d e d 1 : s u s p e n d e d d m a c c h a n n e l 1 c o u n t r e g i s t e r u n d e r f l o w f l a g ( d 1 u f ) 0 : n o u n d e r f l o w 1 : u n d e r f l o w g e n e r a t e d d m a c c h a n n e l 1 s u s p e n d f l a g ( d 1 s f i ) 0 : n o t s u s p e n d e d 1 : s u s p e n d e d d m a c t r a n s f e r s u s p e n d c o n t r o l b i t ( d t s c ) 0 : s u s p e n d i n g o n l y b u r s t t r a n s f e r s d u r i n g i n t e r r u p t p r o c e s s 1 : s u s p e n d i n g b o t h b u r s t a n d c y c l e s t e a l t r a n s f e r s d u r i n g i n t e r r u p t p r o c e s s d m a c r e g i s t e r r e l o a d d i s a b l e b i t ( d r l d d ) 0 : e n a b l i n g r e l o a d o f s o u r c e a n d d e s t i n a t i o n r e g i s t e r s o f b o t h c h a n n e l s 1 : d i s a b l i n g r e l o a d o f s o u r c e a n d d e s t i n a t i o n r e g i s t e r s o f b o t h c h a n n e l s r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) c h a n n e l i n d e x b i t ( d c i ) 0 : c h a n n e l 0 a c c e s s i b l e 1 : c h a n n e l 1 a c c e s s i b l e dmac channel x mode register 1 (address 0040 16 ) dmaxm1 d m a c c h a n n e l x s o u r c e r e g i s t e r i n c r e m e n t / d e c r e m e n t s e l e c t i o n b i t ( d x s r i d ) 0 : i n c r e m e n t a f t e r t r a n s f e r 1 : d e c r e m e n t a f t e r t r a n s f e r d m a c c h a n n e l x s o u r c e r e g i s t e r i n c r e m e n t / d e c r e m e n t e n a b l e b i t ( d x s r c e ) 0 : i n c r e m e n t / d e c r e m e n t d i s a b l e d ( n o c h a n g e a f t e r t r a n s f e r ) 1 : i n c r e m e n t / d e c r e m e n t e n a b l e d d m a c c h a n n e l x d e s t i n a t i o n r e g i s t e r i n c r e m e n t / d e c r e m e n t s e l e c t i o n b i t ( d x d r i d ) 0 : i n c r e m e n t a f t e r t r a n s f e r 1 : d e c r e m e n t a f t e r t r a n s f e r d m a c c h a n n e l x d e s t i n a t i o n r e g i s t e r i n c r e m e n t / d e c r e m e n t e n a b l e b i t ( d x d r c e ) 0 : i n c r e m e n t / d e c r e m e n t d i s a b l e d ( n o c h a n g e a f t e r t r a n s f e r ) 1 : i n c r e m e n t / d e c r e m e n t e n a b l e d d m a c c h a n n e l x d a t a w r i t e c o n t r o l b i t ( d x d w c ) 0 : w r i t i n g d a t a i n r e l o a d l a t c h e s a n d r e g i s t e r s 1 : w r i t i n g d a t a i n r e l o a d l a t c h e s o n l y d m a c c h a n n e l x d i s a b l e a f t e r c o u n t r e g i s t e r u n d e r f l o w e n a b l e b i t ( d x d a u e ) 0 : c h a n n e l x e n a b l e d a f t e r c o u n t r e g i s t e r u n d e r f l o w 1 : c h a n n e l x d i s a b l e d a f t e r c o u n t r e g i s t e r u n d e r f l o w d m a c c h a n n e l x r e g i s t e r r e l o a d b i t ( d x r l d ) 0 : n o t r e l o a d e d ( b i t i s a l w a y s r e a d a s 0 ) 1 : s o u r c e , d e s t i n a t i o n , a n d t r a n s f e r c o u n t r e g i s t e r s c o n t e n t s o f c h a n n e l x t o b e r e l o a d e d d m a c c h a n n e l x t r a n s f e r m o d e s e l e c t i o n b i t ( d x t m s ) 0 : c y c l e s t e a l t r a n s f e r m o d e 1 : b u r s t t r a n s f e r m o d e d m a c c h a n n e l 0 h a r d w a r e t r a n s f e r r e q u e s t s o u r c e b i t s ( d 0 h r ) b 3 b 2 b 1 b 0 0 0 0 0 : n o t u s e d 0 0 0 1 : u a r t 1 r e c e i v e i n t e r r u p t 0 0 1 0 : u a r t 1 t r a n s m i t i n t e r r u p t 0 0 1 1 : t i m e r y i n t e r r u p t 0 1 0 0 : i n t 0 i n t e r r u p t 0 1 0 1 : u s b e n d p o i n t 1 i n _ p k t _ r d y s i g n a l ( f a l l i n g e d g e a c t i v e ) 0 1 1 0 : u s b e n d p o i n t 2 i n _ p k t _ r d y s i g n a l ( f a l l i n g e d g e a c t i v e ) 0 1 1 1 : u s b e n d p o i n t 3 i n _ p k t _ r d y s i g n a l ( f a l l i n g e d g e a c t i v e ) 1 0 0 0 : u s b e n d p o i n t 1 o u t _ p k t _ r d y s i g n a l ( r i s i n g e d g e a c t i v e ) 1 0 0 1 : u s b e n d p o i n t 1 o u t _ f i f o _ n o t _ e m p t y s i g n a l ( r i s i n g e d g e a c t i v e ) 1 0 1 0 : u s b e n d p o i n t 2 o u t _ p k t _ r d y s i g n a l ( r i s i n g e d g e a c t i v e ) 1 0 1 1 : u s b e n d p o i n t 3 o u t _ p k t _ r d y s i g n a l ( r i s i n g e d g e a c t i v e ) 1 1 0 0 : m a s t e r c p u b u s i n t e r f a c e o b e 0 s i g n a l ( r i s i n g e d g e a c t i v e ) 1 1 0 1 : m a s t e r c p u b u s i n t e r f a c e i b f 0 s i g n a l , d a t a ( r i s i n g e d g e a c t i v e ) 1 1 1 0 : s e r i a l i / o t r a s m i t / r e c e i v e i n t e r r u p t 1 1 1 1 : c n t r 1 i n t e r r u p t d m a c c h a n n e l 0 s o f t w a r e t r a n s f e r t r i g g e r ( d 0 s w t ) 0 : n o a c t i o n ( b i t i s a l w a y s r e a d a s 0 ) 1 : r e q u e s t o f c h a n n e l 0 t r a n s f e r b y w r i t i n g 1 ( n o t e 1 ) d m a c c h a n n e l 0 u s b a n d m a s t e r c p u b u s i n t e r f a c e e n a b l e b i t ( d 0 u m i e ) 0 : d i s a b l e d 1 : e n a b l e d d m a c c h a n n e l 0 t r a n s f e r i n i t i a t i o n s o u r c e c a p t u r e r e g i s t e r r e s e t b i t ( d 0 c r r ) 0 : n o a c t i o n ( b i t i s a l w a y s r e a d a s 0 ) 1 : r e s e t o f c h a n n e l 0 c a p t u r e r e g i s t e r b y w r i t i n g 1 ( n o t e 1 ) d m a c c h a n n e l 0 e n a b l e b i t ( d 0 c e n ) 0 : c h a n n e l 0 d i s a b l e d 1 : c h a n n e l 0 e n a b l e d ( n o t e 2 ) d m a c c h a n n e l 0 m o d e r e g i s t e r 2 ( a d d r e s s 0 0 4 1 1 6 ) d m a 0 m 2 dmac channel 1 hardware transfer request source bits (d1hr) b3b2b1b0 0 0 0 0: not used 0 0 0 1: uart2 receive interrupt 0 0 1 0: uart2 transmit interrupt 0 0 1 1: timer x interrupt 0 1 0 0: int 1 interrupt 0 1 0 1: usb endpoint 1 in_pkt_rdy signal (falling edge active) 0 1 1 0: usb endpoint 2 in_pkt_rdy signal (falling edge active) 0 1 1 1: usb endpoint 4 in_pkt_rdy signal (falling edge active) 1 0 0 0: usb endpoint 1 out_pkt_rdy signal (rising edge active) 1 0 0 1: usb endpoint 1 out_fifo_not_empty signal (rising edge active) 1 0 1 0: usb endpoint 2 out_pkt_rdy signal (rising edge active) 1 0 1 1: usb endpoint 4 out_pkt_rdy signal (rising edge active) 1 1 0 0: master cpu bus interface obe 1 signal (rising edge active) 1 1 0 1: master cpu bus interface ibf 1 signal, data (rising edge active) 1 1 1 0: timer 1 trasmit/receive interrupt 1 1 1 1: cntr 0 interrupt dmac channel 1 software transfer trigger (d1swt) 0: no action (bit is always read as 0 ) 1: request of channel 0 transfer by writing 1 ( note 1 ) dmac channel 1 usb and master cpu bus interface enable bit (d1umie) 0: disabled 1: enabled dmac channel 1 transfer initiation source capture register reset bit (d1crr) 0: no action (bit is always read as 0 ) 1: reset of channel 1 capture register by writing 1 ( note 1 ) dmac channel 1 enable bit (d1cen) 0: channel 0 disabled 1: channel 0 enabled ( note 2 ) d m a c c h a n n e l 1 m o d e r e g i s t e r 2 ( a d d r e s s 0 0 4 1 1 6 ) d m a 1 m 2 b 0 b 7 b0 b 7 b0 b7 b0 b7 n o t e s 1 : t h i s b i t i s a u t o m a t i c a l l y c l e a r e d t o 0 a f t e r w r i t i n g 1 . 2 : w h e n s e t t i n g t h i s b i t t o 1 , s i m u l t a n e o u s l y s e t t h e d m a c c h a n n e l x t r a n s f e r i n i t i a t i o n s o u r c e c a p t u r e r e g i s t e r r e s e t b i t ( b i t 6 o f d m a x m 2 ) t o 1 . fig. 32 structure of dmacx related register
7641 group rev.4.00 aug 28, 2006 page 40 of 135 rej03b0191-0400 (1) cycle steal transfer mode when the dmac channel x (x = 0, 1) transfer mode selection bit (dxtms) is set to 0 , the respective dmac channel x operates in the cycle steal transfer mode. when a request of the specified transfer factor is generated, the selected channel transfers one byte of data from the address indi- cated by the source register into the address indicated by the destination register. there are two kinds of dma transfer triggers supported: hardware transfer factor and software trigger. hardware transfer factors can be selected by the dmacx (x = 0, 1) hardware transfer request factor bit (dxhr). to only use the interrupt request bit, the inter- rupt can be disabled by setting its interrupt enable bit of interrupt control register to 0 . the dma transfer request as a software trigger can be generated by setting the dma channel x (x = 0, 1) software transfer trigger bit (dxswt) to 1 . the source registers and transfer destination registers can be either decreased or increased by 1 after transfer completion by setting bits 0 to 3 in the dmac channel x (x = 0, 1) mode regis- ter. when the transfer count register underflows, the source registers and destination registers are reloaded from their latches if the dmac register reload disable bit (drldd) is 0 . the transfer count register value is reloaded after an underflow regardless of drldd setting. at the same time, the dmac inter- rupt request bit and the dma channel x (x = 0, 1) count register underflow flag are set to 1 . the dmac channel x disable after count register underflow en- able bit (dxdaue) is 1 , the dmac channel x enable bit (dxcen) goes to 0 at an under flows of transfer count register. by setting the dmac channel x (x = 0, 1) register reload bit (dxrld) to 1 , the source registers, destination registers, and transfer count registers can be updated to the values in their re- spective latches. when one signal among usb endpoint signals is selected as the hardware transfer request factor, and dmac channel x (x = 0, 1) usb and master cpu bus interface enable bit (dxumie) is 1 ; transfer between the usb fifo and the master cpu bus interface input/output buffer can be performed effectively. this transfer function is only valid in the cycle steal mode. to validate this func- tion, the dmac channel x (x = 0, 1) usb and the master cpu bus interface enable bit (bit 5 of dxtr) must be set to 1 . the follow- ing shows an example of a transfer using this function. packet transfer from usb fifo to master cpu bus interface buffer when the usb out_pkt_rdy is selected as the hardware trans- fer request factor; if the usb out_pkt_rdy is 1 and the master cpu bus interface output buffer is empty, the transfer re- quest is generated and the transfer is initiated. the out_pkt_rdy retains 1 and a transfer request is generated each time the output buffer empties until all the data in the corre- sponding endpoint fifo has been transferred. the transfer ends when the last byte in the usb receive packet is transferred and the out_pkt_rdy flag goes to 0 (in the case of auto_clr bit = 1 ). byte transfer from usb fifo to master cpu bus interface buffer when the usb endpoint 1 out_fifo_not_empty is selected as a hardware transfer request factor, if there is data in the usb endpoint 1 fifo and the master cpu bus interface output buffer is empty; a transfer request is generated and the transfer is initi- ated. the transfer is performed by unit of one byte. transfer from master cpu bus interface buffer to usb fifo when the usb endpoint x (x = 1 to 4) in_pkt_rdy (in_pkt_rdy = 0 ) is selected as a hardware transfer request factor, if there is data in the master cpu bus interface output buffer and the data in the usb fifo is within the specified packet size, a transfer request is generated. the dma transfer is terminated when a command (a0 = 1 ) is in- put to the master cpu bus interface input buffer. the timing chart for a cycle steal transfer caused by a hardware- related transfer request and a software trigger are shown in figure 33 and 34, respectively.
7641 group rev.4.00 aug 28, 2006 page 41 of 135 rej03b0191-0400 o u t s y n c o u t r d wr a 5 a d l 18 5 d m a d a t a ad l 2 a d l 2, 0 0 dma desti- nation add. dma source add. p c + 2 a d l 1 , 0 0 p c + 1 pc p c + 3 pc + 4 lda $zz sta $zz dma transfer s t a $ z z ( l a s t 2 c y c l e s ) d a t a d m a o u t ( p o r t p 3 3 ) a d d r e s s d a t a transfer request source ( l active) t r a n s f e r r e q u e s t s o u r c e s a m p l i n g r e s e t o f t r a n s f e r r e q u e s t s o u r c e s a m p l i n g next instruction o p c o d e 3 data d m a d a t a fig. 33 timing chart for cycle steal transfer caused by hardware-related transfer request 3 c 18 4 1 9 0 42, 00 pc + 2 pc + 1 pc pc + 3 pc + 4 ldm #$90, $41 pc + 6 pc + 5 o u t sync out rd wr d m a o u t ( p o r t p 3 3 ) address data t r a n s f e r r e q u e s t s o u r c e ( l a c t i v e ) t r a n s f e r r e q u e s t s o u r c e s a m p l i n g reset of transfer request source sampling next instruction 1 cycle instruction 1 cycle instruction 1 cycle instruction dma transfer d m a d a t a dma desti- nation add. dma source add. o p c o d e 2 d m a d a t a o p c o d e 3 o p code 4 o p c o d e 6 fig. 34 timing chart for cycle steal transfer caused by software trigger transfer request
7641 group rev.4.00 aug 28, 2006 page 42 of 135 rej03b0191-0400 (2) burst transfer mode when the dmac channel x transfer mode selection bit (dxtms) is set to 1 , the respective dmac channel operates in the burst transfer mode. in the burst transfer mode, the dmac continually transfers the number of bytes of data specified by the transfer count register for one transfer request. other than this, the burst transfer mode operation is the same as the cycle steal mode operation. priority the dmac places a higher priority on channel-0 transfer requests than on channel-1 transfer requests. if a channel-0 transfer request occurs during a channel-1 burst transfer operation, the dmac completes the next transfer source and destination read/write operation first, and then starts the channel-0 transfer operation. as soon as the channel-0 transfer is completed, the dmac resumes the channel-1 transfer operation. when an interrupt request occurs during any dma operation, the transfer operation is suspended and the interrupt process routine is initiated. during the interrupt operation, the dmac automatically sets the corresponding dmac channel x (x = 0, 1) suspend flag (dxsfi) to 1 . as soon as the cpu completes the interrupt opera- tion, the dmac clears the flag to 0 and resumes the original operation from the point where it was suspended. the suspended transfer due to the interrupt can also be resumed during its interrupt process routine by writing 1 to the dmac channel x (x = 0,1) enable bit (dxcen). the timing charts for a burst transfer caused by a hardware-re- lated transfer request are shown in figure 35. fig. 35 timing chart for burst transfer caused by hardware-related transfer request a5 a d l 185 p c + 2 a d l 1 , 0 0 p c + 1 p c pc + 3 lda $zz sta $zz (first cycle) sta $zz ( second c y cle ) o u t s y n c o u t rd wr dma out (port p3 3 ) a d d r e s s d a t a t r a n s f e r r e q u e s t s o u r c e ( l a c t i v e ) t r a n s f e r r e q u e s t s o u r c e s a m p l i n g reset of transfer request source sampling dma transfer d a t a dma destina- tion add. 1 dma source add. 1 dma destina- tion add. 2 dma source add. 2 dma data 1 dma data 1 d m a d a t a 2 dma data 2 a d l 2
7641 group rev.4.00 aug 28, 2006 page 43 of 135 rej03b0191-0400 usb function the 7641 group mcu is equipped with a usb function control unit (usb fcu). this usb fcu allows the mcu to communicate with a host pc using a minimum amount of the mcu power. this built-in usb fcu complies with full-speed usb2.0 specification that supports four transfer types: control transfer, isochronous transfer, interrupt transfer, and bulk transfer. this built-in usb fcu performs the data transfer error detection and transfer retry operation by hardware. the default transfer mode of the usb fcu is bulk transfer mode at reset. the user must set the usb fcu for the required transfer mode by software. the usb fcu has five endpoints (endpoint 0 to endpoint 4). the epindex bit selects one of these five endpoints for the usb fcu to use. each endpoint has in (transmit) fifo and out (receive) fifo. to use the usb fcu, the usb enable bit (usbc7) must be set to 1. there are two usb related interrupts supported for this mcu: usb function interrupt and usb sof interrupt. figure 36 shows the usb fcu (usb function control unit) block diagram. the usb fcu consists of the sie (serial interface en- gine) performing the usb data transfer, gfi (generic function interface) performing usb protocol handing, siu (serial engine interface unit) performing a received address and endpoint de- coding, mci (microcontroller interface) handling the mcu interface or performing address decoding and synchronization of control signals, and the usb transceiver. microcontroller interface unit (mci) s e r i a l e n g i n e i n t e r f a c e u n i t ( s i u ) generic function interface (gfi) f i f o s serial interface engine (sie) t r a n s c e i v e r u s b d + u s b d - cpu fig. 36 usb fcu (usb function control unit) block
7641 group rev.4.00 aug 28, 2006 page 44 of 135 rej03b0191-0400 usb transmission endpoint 0 to endpoint 4 have in (transmit) fifos individually. each endpoint s fifo is configured in following way: endpoint 0: 16-byte endpoint 1: mode 0: 512-byte mode 1: 1024-byte mode 2: 0-byte mode 3: 2048-byte mode 4: 768-byte mode 5: 880-byte endpoint 2: mode 0: 32-byte mode 1: 128-byte endpoint 3: 16-byte endpoint 4: 16-byte when endpoint 1 or endpoint 2 is used for data transmit, the in fifo size can be selected. endpoint 1 and endpoint 2 have pro- grammable in-fifos size; 6 modes for endpoint 1, and 2 modes for endpoint 2. each mode can be selected by the usb endpoint fifo mode selection register (address 005f 16 ). when writing data to the usb endpoint-x fifo (addresses 0060 16 to 0064 16 ) in the sfr area, the internal write pointer for the in fifo is automatically increased by 1. when the auto_set bit is 1 and if the stored data reaches to the max. packet value set in usb endpoint x in max. packet size register (address 005b 16 ), the usb fcu sets the in_pkt_rdy bit to 1 . when the auto_set bit is 0 , the in_pkt_rdy bit will not be automati- cally set to 1 ; it must be set to 1 by software. (the auto_set bit function is not applicable to endpoint 0.) the usb fcu transmits the data when it receives the next in to- ken. the in_pkt_rdy bit automatically goes to 0 when the data transfer is complete. endpoints 1 to 4 can be used in isochronous transfer mode. when using isochronous transfer mode, the iso/toggle_init bit must be set to 1 . when iso_update = 1 and the corresponding endpoint s iso/toggle_init bit = 1 , the usb fcu delays the rise of the in_pkt_rdy bit until the next sof signal transmis- sion. in this way, the usb fcu can synchronize a transmit data to the sof signal. endpoints 1 to 4 can be used in interrupt transfer mode. during a regular interrupt transfer, an interrupt transaction is similar to the bulk transfer. therefore, there is no special setting required. when in-endpoint is used for a rate feedback interrupt transfer, intpt bit of the in_csr register must be set to 1 . the following steps show how to configure the in-endpoint for the rate feedback inter- rupt transfer. 1. set a value which is larger than 1/2 of the usb endpoint-x fifo size to the usb endpoint x in max. package size register. 2. set intpt bit to 1 . 3. flush the old data in the fifo. 4. store transmission data to the in fifo and set the in_pkt_rdy bit to 1 . 5. repeat steps 3 and 4. in a real application, the function-side always has transfer data when the function sends an endpoint in a rate feedback interrupt. accordingly, the usb fcu never returns a nak against the host in token for the rate feedback interrupt. the usb fcu always transmits data in the fifo in response to an in token, regardless of in_pkt_rdy. however, this premises that there is always an ack response from host pc after the 7641 group has transmitted data to in token. when maxp size (a half of in fifo size), the in fifo can store two packets (called double buffer). at this time, the in fifo sta- tus can be checked by monitoring the in_pkt_rdy bit and the tx_not_ept flag. the tx_not_ept flag is a read-only flag which shows the fifo state. when in_pky_rdy = 0 and tx_not_ept = 0, in fifo is empty. when in_pky_rdy = 0 and tx_not_ept = 1, in fifo has one packet. in double buffer mode, as long as the in fifo is not filled with double packets, in_pkt_rdy will not be set to 1 , even if it is set to 1 by software, but tx_not_ept flag will be set to 1 . in single buffer mode, if maxp > (a half of in fifo), this condition never occurs. when in_pkt_rdy = 1 and tx_not_ept = 1 , in fifo holds two packets in double buffer mode and one packet in single packet mode. in single packet mode, when the in_pkt_rdy bit is set to 1 by software, the tx_not_ept flag is set to 1 as well. during double buffer mode, if you want to load two packets se- quentially, you must set the in_pkt_rdy bit to 1 each time a packet is loaded.
7641 group rev.4.00 aug 28, 2006 page 45 of 135 rej03b0191-0400 usb reception endpoint 0 to endpoint 4 have out (receive) fifos individually. each endpoint s fifo is configured in following way: endpoint 0: 16-byte endpoint 1: mode 0: 800-byte mode 1: 1024-byte mode 2: 2048-byte mode 3: 0-byte mode 4: 1280-byte mode 5: 1168-byte endpoint 2: mode 0: 32-byte mode 1: 128-byte endpoint 3: 16-byte endpoint 4: 16-byte when endpoint 1 or endpoint 2 is used for data receive, the out fifo size can be selected. endpoint 1 and endpoint 2 have pro- grammable in-fifos size; 6 modes for endpoint 1, and 2 modes for endpoint 2. each mode can be selected by the usb endpoint fifo mode selection register (address 005f 16 ). data transmitted from the host-pc is stored in endpoint x fifo (0060 16 to 0064 16 ). every time the data is stored in the fifo, the internal out fifo write pointer is increased by 1. when one com- plete data packet is stored, the out_pkt_rdy flag is set to 1 and the number of received data packets is stored in usb end- point x out write count registers (low and high). when the auto_clr bit is 1 and the received data is read out from the out fifo, the out_pkt_rdy flag is cleared to 0 . when the auto_clr bit is 1 , the out_pkt_rdy flag will not be cleared automatically by the fifo read; it must be cleared by software. (the auto-clr bit function is not applicable in endpoint 0.) when maxp size (a half of out fifo size), the out_fifo can receive 2 packets (double buffer). at this time, the out_ fifo sta- tus can be checked by the out_pkt_rdy flag. when the fifo holds two packets and one packet is read from the fifo, the out_pkt_rdy flag is not cleared even if it is set to 0 . (the flag returns from 0 to 1 in one cycle after the read-out). during double buffer mode, the usb endpoint x out write count regis- ters (low and high) holds the number of previously received packets. this count register is updated after reading out one of packets in the out fifo and clearing the out_pkt_rdy flag to 0 . toggle initialization in order to initialize the data toggle sequence bit of the endpoint, in other words, resetting the next data packet to data0; set the iso/toggle_int bit to 1 and then clear back to 0 .
7641 group rev.4.00 aug 28, 2006 page 46 of 135 rej03b0191-0400 usb interrupts the usb fcu has two interrupts, usb function interrupt and usb sof (start of frame) interrupt. the usbf-int is usable for the usb data flow control and power management. the usbf-int request occurs at data transmit/re- ceive completion, overrun/underrun, reset, or receiving suspend/ resume signal. to enable this interrupt, the usb function interrupt enable bit in the interrupt control register a (address 0005 16 ) and the respective bit in the usb interrupt enable registers 1 and 2 (addresses 00054 16 and 00055 16 ) must be set to 1 . when set- ting bit 7 in usb interrupt enable register 2 to 1 , the suspend interrupt and the resume interrupt are enabled. endpoint x (x = 0 to 4) in interrupt request occurs when the usb endpoint x in interrupt status flag (intst 0, 2, 4, 6, 8) of usb in- terrupt status registers 1 and 2 (addresses 0052 16 and 0053 16 ) is 1 . the usb endpoint x in interrupt status flag is set to 1 when the respective endpoint in_pkt_rdy bit is 1 . endpoint x (x = 0 to 4) out interrupt request occurs when the usb endpoint x out interrupt status flag (intst3, 5, 7, 9) in usb interrupt status registers 1 and 2 is set to 1 . the usb endpoint x out interrupt status flag is set to 1 when the respective endpoint out_pkt_rdy flag is 1 . the overrun/underrun interrupt request occurs when the usb overrun/underrun interrupt status flag (intst12) in usb interrupt status register 2 is set to 1 . this flag is set to 1 when the fifo data overruns or underruns in isochronous transfer mode. the usb reset interrupt request occurs when the usb reset inter- rupt status flag (intst13) in usb interrupt status register 2 is set to 1 . this flag is set when the se0 is detected on the d+/d- line for at least 2.5 s. when this situation happens, all usb internal registers (addresses 0050 16 to 005f 16 ), except this flag, are ini- tialized to the default state at reset. the usb reset interrupt is always enabled. the suspend/resume interrupt request occurs when either the usb resume signal interrupt status flag (intst14) or the usb suspend signal interrupt status flag (intst15) in usb interrupt status register 2 is set to 1 . the bits in both interrupt status registers 1 and 2 can be cleared by writing 1 to each bit. the usb sof interrupt is usable in isochronous transfers. this in- terrupt request occurs when an sof packet is received. to enable a usb sof interrupt, set the usb sof interrupt enable bit of in- terrupt control register a to 1 . suspend/resume functions if no bus activity is detected on the d+/d- line for at least 3 ms, the usb suspend signal detect flag (suspend) of the usb power control register (address 0051 16 ) and the usb suspend signal in- terrupt status flag of usb interrupt status register 2 are set to 1 and the suspend interrupt request occurs. the following procedure must be executed after pushing the internal registers (a, x, y ) to memories during the suspend interrupt process routine. (1) clear all bits of usb interrupt status register 1 (address 0052 16 ) and usb interrupt status register 2 (address 0053 16 ) to 0 . (2) set the usb clock enable bit to 0 . (after disabling the usb clock, do not write to any of the usb internal registers (ad- dresses 0050 16 to 0064 16 ), except for the usb control register (address 0013 16 ), clock control register (address 001f 16 ), and frequency synthesizer control register (address 006c 16 ). (3) set the frequency synthesizer enable bit to 0 . (4) set the usb line driver current control bit to 1 . (always keep the usb line driver current control bit set to 0 during usb function operations. when operating at vcc = 3.3 v, this bit does not need to be set.) (5) keep total drive current at 500 a or less. (6) disable the timer 1 interrupt. (7) disable the timer 2 interrupt. (disable all the other external in- terrupts.) (8) set the timer 1 interrupt request bit to 0 . (9) set the timer 2 interrupt request bit to 0 . (10) set the interrupt disable flag (i) to 0 . (11) execute the stp instruction. at this point, the mcu will be in stop mode (suspend mode). be- fore executing the stp instruction, make sure to set the usb function interrupt request bit (bit 0 at address 0002 16 ) to 0 and the usb function interrupt enable bit (bit 0 at address 0005 16 ) to 1 .
7641 group rev.4.00 aug 28, 2006 page 47 of 135 rej03b0191-0400 the usb suspend detect signal flag goes to 0 when the usb re- sume signal detect flag (resume) is set to 1 . during suspend mode, if the clock operation is started up with a process (remote wake-up) other than the resume interrupt process (for example; reset or timer), make sure to clear the usb suspend detect signal flag to 0 when you set the usb remote wake-up bit to 1 . when the usb fcu is in suspend mode and detects a non-idle signal on the d+/d- line, the usb resume detect flag and the usb resume signal interrupt status flag both go to 1 and a resume interrupt request occurs. at this point, pull the internal registers (a, x, y) in this interrupt process routine. take the following procedure in the usb resume interrupt process. (1) set the usb line driver current control bit to 0 . (when operat- ing at vcc = 3.3 v, this bit does not need to be set.) (2) set the frequency synthesizer enable bit to 1 and set a 2 ms to 5 ms wait. (3) check the frequency synthesizer lock status bit. if 0 , it must be checked again after a 0.1 ms wait. (4) enable the usb clock. fig. 37 structure of usb control register usb control register (address 0013 16 ) usbc reserved bit ( 0 at read/write) usb default state selection bit (usbc1) 0: in default state after power-on/reset 1: in default state after usb reset signal received usb artificial sof enable bit (usbc2) 0: artificial sof disabled 1: artificial sof enabled usb line driver current control bit (usbc3) 0: high current mode 1: low current mode usb line driver supply enable bit (usbc4) ( note 1 ) 0: line driver disabled 1: line driver enabled usb clock enable bit (usbc5) 0: 48 mhz clock to the usb block disabled 1: 48 mhz clock to the usb block enabled usb sof port select bit (usbc6) 0: sof output disabled 1: sof output enabled usb enable bit (usbc7) 0: usb block disabled ( note 2 ) 1: usb block enabled n o t e s 1 : w h e n u s i n g t h e m c u i n v c c = 3 . 3 v , s e t t h i s b i t t o 0 a n d d i s a b l e t h e b u i l t - i n d c - d c c o n v e r t e r 2 : s e t t i n g t h i s b i t t o 0 c a u s e s t h e c o n t e n t s o f a l l u s b r e g i s t e r s t o h a v e t h e v a l u e s a t r e s e t . b 0 b 7 0 set the usb resume signal interrupt status flag to 0 after the wake-up sequence process. the usb resume detect flag goes to 0 at the same time. when the clock operation is started up with a remote wake-up, set the usb remote wake-up bit to 1 after the wake-up sequence process. (keep it set to 1 for a minimum of 10 ms and maximum of 15 ms). by doing this, the mcu will send a resume signal to the host cpu and let it know that the suspend state has been released. after that, set the usb remote wake-up bit and the usb suspend detection flag to 0 , because the usb suspend detection flag is not automatically cleared to 0 with a remote wake-up. [usb control register] usbc when using the usb function, the usb enable bit must be set to 1 . the usb line driver supply bit must be set to 0 (dc-dc con- verter is disabled) when operating at vcc = 3.3v. in this condition, the setting of the usb line driver current control bit has no effect on usb operations. when the usb artificial sof enable bit is set to 1 , the mcu judges that a sof packet is received within 250 ns from a frame starting if an sof packet is destroyed owing to some cause.
7641 group rev.4.00 aug 28, 2006 page 48 of 135 rej03b0191-0400 [usb address register] usba the usb address register maintains the usb function control unit address assigned by the host computer. when receiving the set_address, keep it in this register. the values of this register are 0 when the device is not yet configured. the values of this register are also set to 0 when the usb block is disabled (bit 7 of usb control register is set to 0 ). in addition, no matter what value is written to this register, it will have no effect on the set value. [usb power management register] usbpm the usb power management register is used for power manage- ment in the usb fcu. this register needs to be set only when using the remote wake-up to resume the mcu from suspend mode. usb address register (address 0050 16 ) usba programmable function address (funad0 to 6)) this register maintains the 7-bit usb function control unit address assigned by the host cpu. reserved bit ( 0 at read/write) b 0 b 7 0 u s b p o w e r m a n a g e m e n t r e g i s t e r ( a d d r e s s 0 0 5 1 1 6 ) u s b p m u s b s u s p e n d d e t e c t i o n f l a g ( s u s p e n d ) ( r e a d o n l y ) 0 : n o u s b s u s p e n d d e t e c t e d 1 : u s b s u s p e n d d e t e c t e d u s b r e s u m e d e t e c t i o n f l a g ( r e s u m e ) ( r e a d o n l y ) 0 : n o u s b r e s u m e s i g n a d e t e c t e d 1 : u s b r e s u m e s i g n a l d e t e c t e d u s b r e m o t e w a k e - u p b i t ( w a k e u p ) 0 : e n d o f r e m o t e r e s u m e s i g n a l 1 : t r a n s m i t t i n g o f r e m o t e r e s u m e s i g n a l ( o n l y w h e n s u s p e n d = 1 ) r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) b 0 b 7 00000 fig. 38 structure of usb address register fig. 39 structure of usb power management register
7641 group rev.4.00 aug 28, 2006 page 49 of 135 rej03b0191-0400 [usb interrupt status registers 1 and 2] usbis1, usbis2 the usb interrupt status registers are used to indicate the condi- tion that caused a usb function interrupt to be generated. each status flag and bit can be cleared to 0 by writing 1 to the corre- sponding bit. make sure to write to/read from the usb interrupt status register 1 first and then usb interrupt status register 2. when an in token is received during an isochronous transfer, and u s b i n t e r r u p t s t a t u s r e g i s t e r 1 ( a d d r e s s 0 0 5 2 1 6 ) u s b i s 1 u s b e n d p o i n t 0 i n t e r r u p t s t a t u s f l a g ( i n t s t 0 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t a n y o n e o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 0 i s s u c c e s s f u l l y r e c e i v e d ? a p a c k e t d a t a o f e n d p o i n t 0 i s s u c c e s s f u l l y s e n t ? d a t a _ e n d b i t o f e n d p o i n t 0 i s c l e a r e d t o 0 ? f o r c e _ s t a l l b i t o f e n d p o i n t 0 i s s e t t o 1 ? s e t u p _ e n d b i t o f e n d p o i n t 0 i s s e t t o 1 . r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) u s b e n d p o i n t 1 i n i n t e r r u p t s t a t u s f l a g ( i n t s t 2 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t w h i c h o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 1 i s s u c c e s s f u l l y s e n t ? u n d e r _ r u n b i t o f e n d p o i n t 1 i s s e t t o 1 . u s b e n d p o i n t 1 o u t i n t e r r u p t s t a t u s f l a g ( i n t s t 3 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t a n y o n e o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 1 i s s u c c e s s f u l l y r e c e i v e d ? o v e r _ r u n b i t o f e n d p o i n t 1 i s s e t t o 1 ? f o r c e _ s t a l l b i t o f e n d p o i n t 1 i s s e t t o 1 . u s b e n d p o i n t 2 i n i n t e r r u p t s t a t u s f l a g ( i n t s t 4 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t w h i c h o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 2 i s s u c c e s s f u l l y s e n t ? u n d e r _ r u n b i t o f e n d p o i n t 2 i s s e t t o 1 . u s b e n d p o i n t 2 o u t i n t e r r u p t s t a t u s f l a g ( i n t s t 5 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t a n y o n e o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 2 i s s u c c e s s f u l l y r e c e i v e d ? o v e r _ r u n b i t o f e n d p o i n t 2 i s s e t t o 1 ? f o r c e _ s t a l l b i t o f e n d p o i n t 2 i s s e t t o 1 . u s b e n d p o i n t 3 i n i n t e r r u p t s t a t u s f l a g ( i n t s t 6 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t w h i c h o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 3 i s s u c c e s s f u l l y s e n t ? u n d e r _ r u n b i t o f e n d p o i n t 3 i s s e t t o 1 . u s b e n d p o i n t 3 o u t i n t e r r u p t s t a t u s f l a g ( i n t s t 7 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n s 1 : s e t a t a n y o n e o f t h e f o l l o w i n g c o n d i t i o n s : ? a p a c k e t d a t a o f e n d p o i n t 3 i s s u c c e s s f u l l y r e c e i v e d ? o v e r _ r u n b i t o f e n d p o i n t 3 i s s e t t o 1 ? f o r c e _ s t a l l b i t o f e n d p o i n t 3 i s s e t t o 1 . b0 b7 0 the in fifo is empty, an underrun error occurs and intst12 and in_csr2 are set to 1 . when an out token is received and the out fifo is full, an overrun error occurs and intst12 and out_csr2 are set to 1 . underruns and overruns are not de- tected by the cpu in bulk transfers and normal interrupt transfers, however in this case, the mcu will send a nak signal to the host cpu. fig. 40 structure of usb interrupt status register 1
7641 group rev.4.00 aug 28, 2006 page 50 of 135 rej03b0191-0400 fig. 41 structure of usb interrupt status register 2 u s b i n t e r r u p t s t a t u s r e g i s t e r 2 ( a d d r e s s 0 0 5 3 1 6 ) u s b i s 2 usb endpoint 4 in interrupt status flag (intst8) 0: except the following conditions 1: set at which of the following conditions: ? a packet data of endpoint 4 is successfully sent ? under_run bit of endpoint 4 is set to 1 . usb endpoint 4 out interrupt status flag (intst9) 0: except the following conditions 1: set at any one of the following conditions: ? a packet data of endpoint 4 is successfully received ? over_run bit of endpoint 4 is set to 1 ? force_stall bit of endpoint 4 is set to 1 . reserved bit ( 0 at read/write) usb overrun/underrun interrupt status flag (intst12) 0: except the following condition 1: set at an occurrence of overrun/underrun (for isochronous data transfer) usb reset interrupt status flag (intst13) 0: except the following condition 1: set at receiving of usb reset signal usb resume signal interrupt status flag (intst14) 0: except the following condition 1: set at receiving of resume signal usb suspend signal interrupt status flag (intst15) 0: except the following condition 1: set at receiving of suspend signal b 0 b 7 00
7641 group rev.4.00 aug 28, 2006 page 51 of 135 rej03b0191-0400 [usb interrupt enable registers 1 and 2] usbie1, usbie2 the usb interrupt enable registers are used to enable the usb usb interrupt enable register 1 (address 0054 16 ) usbie1 usb endpoint 0 interrupt enable bit (inten0) 0: disabled 1: enabled reserved bit ( 0 at read/write) usb endpoint 1 in interrupt enable bit (inten2) 0: disabled 1: enabled usb endpoint 1 out interrupt enable bit (inten3) 0: disabled 1: enabled usb endpoint 2 in interrupt enable bit (inten4) 0: disabled 1: enabled usb endpoint 2 out interrupt enable bit (inten5) 0: disabled 1: enabled usb endpoint 3 in interrupt enable bit (inten6) 0: disabled 1: enabled usb endpoint 3 out interrupt enable bit (inten7) 0: disabled 1: enabled b0 b 7 0 usb interrupt enable register 2 (address 0055 16 ) usbie2 u s b e n d p o i n t 4 i n i n t e r r u p t e n a b l e b i t ( i n t e n 8 ) 0 : d i s a b l e d 1 : e n a b l e d u s b e n d p o i n t 4 o u t i n t e r r u p t e n a b l e b i t ( i n t e n 9 ) 0 : d i s a b l e d 1 : e n a b l e d r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) u s b o v e r r u n / u n d e r r u n i n t e r r u p t e n a b l e b i t ( i n t e n 1 2 ) 0 : d i s a b l e d 1 : e n a b l e d r e s e r v e d b i t ( 1 a t r e a d / w r i t e ) r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) u s b s u s p e n d / r e s u m e i n t e r r u p t e n a b l e b i t ( i n t e n 1 5 ) 0 : d i s a b l e d 1 : e n a b l e d b 0 b 7 00 01 function interrupt. upon reset, all usb interrupts except the usb suspend and usb resume interrupts are enabled. fig. 42 structure of usb interrupt enable register 1 fig. 43 structure of usb interrupt enable register 2
7641 group rev.4.00 aug 28, 2006 page 52 of 135 rej03b0191-0400 [usb frame number registers low and high ] usbsofl, usbfofh these 11-bit registers contain the frame number of the sof token received from the host computer. these are read-only registers. [usb endpoint index register] usbindex this register specifies the accessible endpoint. it serves as an in- dex to endpoint-specific usb endpoint x in control register, usb endpoint x out control register, usb endpoint x in max. packet size register, usb endpoint x out max. packet size register, usb endpoint x out write count register, and usb fifo mode selection register (x = 0 to 4). usb frame number register low (address 0056 16 ) usbsofl low-order 8 bits of sof token high-order 3 bits of sof token reserved bit ( 0 at read) usb frame number register high (address 0057 16 ) usbsofh b 0 b 7 b 0 b 7 u s b e n d p o i n t i n d e x r e g i s t e r ( a d d r e s s 0 0 5 8 1 6 ) u s b i n d e x endpoint index bit (epindex) b2b1b0 0 0 0: endpoint 0 0 0 1: endpoint 1 0 1 0: endpoint 2 0 1 1: endpoint 3 1 0 0: endpoint 4 1 0 1: not used 1 1 0: not used 1 1 1: not used reserved bit ( 0 at read/write) auto_flush bit (auto_fl) 0: auto fifo flush disabled 1: auto fifo flush enabled iso_update bit (iso_upd) 0: iso_update disabled 1: iso_update enabled b0 b 7 000 fig. 44 structure of usb frame number registers fig. 45 structure of usb frame number registers
7641 group rev.4.00 aug 28, 2006 page 53 of 135 rej03b0191-0400 [usb endpoint 0 in control register ] in_csr this register contains the control and status information of the endpoint 0. this usb fcu sets the out_pkt_rdy flag to 1 upon having received a data packet in the out fifo. when read- ing its one data packet from the out fifo, be sure to set this flag to 0 . after a setup token is received, the mcu is in the decode wait state until the out_pkt_rdy flag is cleared. if the out_pkt_rdy flag is not cleared (indicating that the host re- quest has not been successfully decoded), the usb fcu keep returning a nak to the host for all in/out tokens. set the in_pkt_rdy bit to 1 after the data packet has been written to the in fifo. if this bit is set to 1 even though nothing has been written to the in fifo, a 0 length data (null packet) is sent to the host. the send_stall bit is for sending a stall to the host if an unsupported request is received by the usb fcu. this bit must be set to 1 . when the out_pkt_rdy flag is set to 0 for request reception, the usb fcu transmits a stall signal to the host cpu. perform the following three processes simulta- neously: ? set send_stall bit to 1 ? set data_end bit to 1 ? set out_pkt_rdy flag to 0 by setting serviced_out _pkt_rdy bit to 1 . note that if 0 is written to the send_stall bit before the clear_feature (endpoint stall) request has been received, the next stall will not be generated. the data_end bit informs the usb fcu of the completion of the process indicated in the setup packet. set this bit to 1 when the process requested in the setup packet is completed. (con- trol read transfer: set this bit after writing all of the requested data to the fifo; control write transfer: set this bit to 1 after reading all of the requested data from the fifo.) when this bit is 1 , the host request is ignored and a stall is returned. after the status phase process is completed, the usb fcu automatically clears it to 0 . u s b e n d p o i n t 0 i n c o n t r o l r e g i s t e r ( a d d r e s s 0 0 5 9 1 6 ) i n _ c s r out_pkt_rdy flag (in0csr0) 0: except the following condition (cleared to 0 by writing 1 into serviced_out_pkt_rdy bit) 1: end of a data packet reception in_pkt_rdy bit (in0csr1) 0: end of a data packet transmission 1: write 1 at completion of writing a data packet into in fifo. send_stall bit (in0csr2) 0: except the following condition 1: transmitting stall handshake signal data_end bit (in0csr3) 0: except the following condition (cleared to 0 after completion of status phase) 1: write 1 at completion of writing or reading the last data packet to/from fifo. force_stall flag (in0csr4) 0: except the following condition 1: protocol error detected setup_end flag (in0csr5) ( note ) 0: except the following condition (cleared to 0 by writing 1 into serviced_setup_end bit) 1: control transfer ends before the specific length of data is transferred during the data phase. serviced_out_pkt_rdy bit (in0csr6) writing 1 to this bit clears out_pkt_rdy flag to 0 . serviced_setup_end bit (in0csr7) writing 1 to this bit clears setup_end flag to 0 . b 0 b 7 n o t e : i f t h i s b i t i s s e t t o 0 , s t o p a c c e s s i n g t h e f i f o t o s e r v e t h e p r e v i o u s s e t u p t r a n s a c t i o n . fig. 46 structure of usb endpoint 0 in control register
7641 group rev.4.00 aug 28, 2006 page 54 of 135 rej03b0191-0400 [usb endpoint x (x = 1 to 4) in control register] in_csr this register contains the control and status information of the re- spective in endpoints 1 to 4. set the in_pkt_rdy bit to 1 after the data packet has been written to the in fifo. this bit is cleared to 0 when the data transfer is completed. in a bulk in transfer, this bit is cleared when an ack signal is received from the host. if an ack signal is not re- ceived, this bit (and the tx_not_empty bit) remains as 1. this same data packet is sent after the next in token is received. the flush bit is for flushing the data in the in fifo. u s b e n d p o i n t x i n c o n t r o l r e g i s t e r ( a d d r e s s 0 0 5 9 1 6 ) i n _ c s r i n t _ p k t _ r d y b i t ( i n x c s r 0 ) 0 : e n d o f a d a t a p a c k e t t r a n s m i s s i o n ( n o t e 1 ) 1 : w r i t e 1 a t c o m p l e t i o n o f w r i t i n g a d a t a p a c k e t i n t o i n f i f o . ( n o t e 3 ) u n d e r _ r u n f l a g ( i n x c s r 1 ) ( i n i s o c h r o n o u s d a t a t r a n s f e r ) 0 : n o f i f o u n d e r r u n ( n o t e 2 ) 1 : f i f o u n d e r r u n o c c u r r e d ( n o t e 1 ) ( u s b o v e r r u n / u n d e r r u n i n t e r r u p t s t a t u s f l a g i s s e t t o 0 . ) s e n d _ s t a l l b i t ( i n x c s r 2 ) ( n o t e 2 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n 1 : t r a n s m i t t i n g s t a l l h a n d s h a k e s i g n a l i s o / t o g g l e _ i n i t b i t ( i n x c s r 3 ) ( n o t e 2 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n 1 : i n i t i a l i z i n g t o e n d p o i n t u s e d f o r i s o c h r o n o u s t r a n s f e r ; i n i t i a l i z i n g t h e d a t a t o g g l e s e q u e n c e b i t i n t p t b i t ( i n x c s r 4 ) ( n o t e 2 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n 1 : i n i t i a l i z i n g t o e n d p o i n t u s e d f o r i n t e r r u p t t r a n s f e r , r a t e f e e d b a c k t x _ n o t _ e p t f l a g ( i n x c s r 5 ) ( n o t e 1 ) 0 : e m p t y i n i n f i f o 1 : f u l l i n i n f i f o f l u s h b i t ( i n x c s r 6 ) 0 : e x c e p t t h e f o l l o w i n g c o n d i t i o n ( n o t e 1 ) 1 : f l u s h f i f o . ( n o t e 2 ) a u t o _ s e t b i t ( i n x c s r 7 ) ( n o t e 2 ) 0 : a u t o _ s e t d i s a b l e d 1 : a u t o _ s e t e n a b l e d ( n o t e 4 ) b 0 b 7 notes 1 : this bit is automatically set to 1 or cleared to 0 . 2 : the user must program to 1 or 0 . 3 : when auto_set bit is 0 , the user must set to 1 . when auto_set bit is 1 , this bit is automatically set to 1 . 4 : to use the auto_set function for an in transfer when the auto_set bit is set to 1 , set the fifo to single buffer mode. fig. 47 structure of usb endpoint x (x = 1 to 4) in control register
7641 group rev.4.00 aug 28, 2006 page 55 of 135 rej03b0191-0400 [usb endpoint x (x = 1 to 4) out control register] out_csr this register contains the information and status of the respective out endpoints 1 to 4. in the endpoint 0, all bits are reserved and cannot be used (they will all be read out as 0 ). the usb fcu sets the out_pkt_rdy flag to 1 after a data packet has been received into the out fifo. after reading the data packet in the out fifo, clear this flag to 0 . however, if there is still data in the out fifo, the flag cannot be cleared even by writing 0 by soft- ware. u s b e n d p o i n t x o u t c o n t r o l r e g i s t e r ( a d d r e s s 0 0 5 a 1 6 ) o u t _ c s r out_pkt_rdy flag (outxcsr0) 0: except the following condition ( note 3 ) 1: end of a data packet reception ( note 2 ) over run flag (outxcsr1) (in isochronous data transfer) 0: no fifo overrun ( note 2 ) 1: fifo overrun occurred ( note 1 ) send_stall bit (outxcsr2) ( note 2 ) 0: except the following condition 1: transmitting stall handshake signal iso/toggle_init bit (outxcsr3) ( note 2 ) 0: except the following condition 1: initializing to endpoint used for isochronous transfer; enabling reception of data0 and data1 as pid (initializing the toggle) force_stall flag (outxcsr4) 0: except the following condition ( note 2 ) 1: protocol error detected ( note 1 ) data_err flag (outxcsr5) 0: except the following condition ( note 2 ) 1: crc or bit stuffing error detected in transferring isochronous data ( note 1 ) flush bit (outxcsr6) 0: except the following condition ( note 1 ) 1: flush fifo. ( note 2 ) auto_clr bit (outxcsr7) ( note 2 ) 0: auto_clr disabled 1: auto_clr enabled b0 b7 notes 1 : this bit is automatically set to 1 or cleared to 0 . 2 : the user must program to 1 or 0 . 3 : when auto_clr bit is 0 , the user must clear to 0 . when auto_clr bit is 1 , this bit is automatically cleared to 0 . fig. 48 structure of usb endpoint x (x = 1 to 4) out control register
7641 group rev.4.00 aug 28, 2006 page 56 of 135 rej03b0191-0400 [usb endpoint x (x = 0 to 4) in max. packet size register] in_maxp this register specifies the maximum packet size (maxp) of an endpoint x in packet. the value set for endpoint 1 is the number of transmitted bytes divided by 8, and the value set for endpoints 0, 2, 3, and 4 is the actual number of transmitted bytes. the cpu can change these values using the set_descriptor com- mand. the initial value for endpoints 0, 2, 3 and 4 is 8, and the initial value for endpoint 1 is 1. [usb endpoint x (x = 0 to 4) out max. packet size register] out_maxp this register specifies the maximum packet size (maxp) of an endpoint x out packet. the value set for endpoint 1 is the num- ber of received bytes divided by 8, and the value set for endpoints 0, 2, 3, and 4 is the actual number of received bytes. the cpu can change these values using the set_descriptor com- mand. the initial value for endpoints 0, 2, 3, and 4 is 8, and the initial value for endpoint 1 is 1. when using the endpoint 0, both usb endpoint x in max. packet size register (in _maxp) and usb end- point x out max. packet size register (out_maxp) are set to the same value. changing one register s value effectively changes the value of the other register as well. t h e m a x i m u m p a c k e t s i z e ( m a x p ) o f e n d p o i n t x i n i s c o n t a i n e d . m a x p = n f o r e n d p o i n t s 0 , 2 , 3 , 4 m a x p = n ? 8 f o r e n d p o i n t 1 n i s a w r i t t e n v a l u e i n t o t h i s r e g i s t e r . usb endpoint x in max. packet size register (address 005b 16 ) in_maxp b0 b 7 the maximum packet size (maxp) of endpoint x out is contained. maxp = n for endpoints 0, 2, 3, 4 maxp = n ? 8 for endpoint 1 n is a written value into this register. usb endpoint x out max. packet size register (address 005c 16 ) out_maxp b 0 b 7 fig. 49 structure of usb endpoint x in max. packet size register fig. 50 structure of usb endpoint x out max. packet size register
7641 group rev.4.00 aug 28, 2006 page 57 of 135 rej03b0191-0400 [usb endpoint x (x = 0 to 4) out write count registers (low and high)] wrt_cntrl, wrt_cnth these registers contain the number of bytes in the endpoint x out fifo. these are read-only registers. these two registers must be read after the usb fcu has received a packet of data from the host. when reading these registers, the lower byte must be read first, then the higher byte. when the out fif0 is in double buffer mode, the cpu first reads the received number of bytes of the former data packet. the next cpu read can obtain that of the new data packet. fig. 51 structure of usb endpoint x (x = 0 to 4) out write count registers l o w - o r d e r 8 b i t s o f t h e n u m b e r o f b y t e s i n e n d p o i n t x o u t f i f o u s b e n d p o i n t x o u t w r i t e c o u n t r e g i s t e r l o w ( a d d r e s s 0 0 5 d 1 6 ) w r t _ c n t l b 0 b 7 h i g h - o r d e r 2 b i t s o f t h e n u m b e r o f b y t e s i n e n d p o i n t x o u t f i f o n o t u s e d ( 0 a t r e a d ) usb endpoint x out write count register high (address 005e 16 ) wrt_cnth b 0 b 7 [usb endpoint x (x = 0 to 4) fifo register] usbfifox these registers are the usb in (transmit) and out (receive) fifo data registers. write data to the corresponding register, and read data from the corresponding register. when the maximum packet size is equal to or less than half the fifo size, these registers function in double buffer mode and can hold two packets of data. when the in_pkt_rdy bit is 0 and the tx_not_empty bit is 1 , these bits indicate that one packet of data is stored in the in fifo. when the out fifo is in double buffer mode, the out_pkt_rdy flag remains as 1 after the first packet of data is read out (it actually goes to 0 and returns to 1 after one cycle). en d p o i n t x i n / o u t f i f o usb endpoint x fifo register (addresses 0060 16 , 0061 16 , 0062 16 , 0063 16 , 0064 16 ,) usbfifox b0 b 7 fig. 52 structure of usb endpoint x (x = 0 to 4) fifo register
7641 group rev.4.00 aug 28, 2006 page 58 of 135 rej03b0191-0400 [usb endpoint fifo mode selection register] usbfifomr this register determines in/out fifo size mode for endpoint 1 or endpoint 2. this register is invalid when using endpoint 0, 3, or 4. u s b e n d p o i n t f i f o m o d e r e g i s t e r ( a d d r e s s 0 0 5 f 1 6 ) u s b f i f o m r f i f o s i z e s e l e c t i o n b i t ( n o t e ) f o r e n d p o i n t 1 b 3 b 2 b 1 b 0 x 0 0 0 : i n 5 1 2 - b y t e , o u t 8 0 0 - b y t e x 0 0 1 : i n 1 0 2 4 - b y t e , o u t 1 0 2 4 - b y t e x 0 1 0 : i n 0 - b y t e , o u t 2 0 4 8 - b y t e x 0 1 1 : i n 2 0 4 8 - b y t e , o u t 0 - b y t e x 1 0 0 : i n 7 6 8 - b y t e , o u t 1 2 8 0 - b y t e x 1 0 1 : i n 8 8 0 - b y t e , o u t 1 1 6 8 - b y t e f o r e n d p o i n t 2 0 x x x : i n 3 2 - b y t e , o u t 3 2 - b y t e 1 x x x : i n 1 2 8 - b y t e , o u t 1 2 8 - b y t e r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) b0 b 7 0000 n o t e : t h e v a l u e s e t i n t o x i s i n v a l i d . fig. 53 structure of usb endpoint fifo mode register
7641 group rev.4.00 aug 28, 2006 page 59 of 135 rej03b0191-0400 fig. 54 interrupt request circuit of data bus buffer master cpu bus interface the 7641 group internally has a 2-byte bus interface which control signals from the host cpu side can operate (slave mode). this bus interface allows the 7641 group to be directly connected with a r/w type of cpu bus or a rd and wr separated type of cpu bus. figure 56 shows the block diagram of master cpu bus interface function. the data bus buffer function i/o pins (p5 2 C p5 7 , p6, p7 2 C p7 4 ) also function as the normal i/o ports. when the master cpu bus interface enable bit of data bus buffer control register (bit 6 of address 004a 16 ) is 0 , these pins become the normal i/o ports. when it is 1 , these pins become the master cpu bus interface function pins. additionally, when using the master cpu bus interface function, set port p6 to input mode by setting 00 16 into its port direction register (address 0015 16 ). the selection of either the single data bus buffer mode, which uses 1 byte: data bus buffer 0 only, or the double data bus buffer mode, which uses 2 bytes: data bus buffer 0 and data bus buffer 1, is performed by the data bus buffer function select bit of data bus buffer control register 1 (bit 7 of address 004e 16 ). port p7 2 becomes s 1 input pin in the double data bus buffer mode. when data is written from the host cpu side, an input buffer full interrupt occurs. when data is read from the host cpu, an output buffer empty interrupt occurs. the 7641 group shares two input buffer full interrupt requests and two output buffer empty interrupt requests as shown in figure 54, respectively. the 7641 group can also operate the master cpu bus interface connecting with the built-in dmac. this could transfer a large amount of data fast. an input signal level of data bus buffer function input pins can be selected between a cmos level and a ttl level. set it using the master cpu bus input level select bit of port control register (address 0010 16 ) . i n p u t b u f f e r f u l l f l a g 0 i b f 0 i n p u t b u f f e r f u l l f l a g 1 i b f 1 rising edge detection circuit one-shot pulse generating circuit o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t input buffer full interrupt request signal ibf output buffer full flag 0 obf 0 o u t p u t b u f f e r f u l l f l a g 1 o b f 1 one-shot pulse generating circuit o n e - s h o t p u l s e g e n e r a t i n g c i r c u i t output buffer empty interrupt request signal obe interrupt request is set at this rising edge i n t e r r u p t r e q u e s t i s s e t a t t h i s r i s i n g e d g e i b f 0 i b f 1 i b f o b f 0 ( o b e 0 ) o b f 1 ( o b e 1 ) o b e o b e 0 o b e 1 rising edge detection circuit rising edge detection circuit r i s i n g e d g e d e t e c t i o n c i r c u i t
7641 group rev.4.00 aug 28, 2006 page 60 of 135 rej03b0191-0400 fig. 55 structure of master cpu bus interface related registers data bus buffer status register 0 (address 0049 16 ) dbbs0 o u t p u t b u f f e r f u l l f l a g ( o b f 0 ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l i n p u t b u f f e r f u l l f l a g ( i b f 0 ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l u s e r d e f i n a b l e f l a g ( u 2 ) t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . a 0 f l a g ( a 00 ) t h i s f l a g i n d i c a t e s t h e c o n d i t i o n o f a 0 s t a t u s w h e n t h e i b f 0 f l a g i s s e t . u s e r d e f i n a b l e f l a g ( u 4 C u 7 ) t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . b 0 b 7 data bus buffer control register 0 (address 004a 16 ) dbbc0 o b f 0 o u t p u t e n a b l e b i t 0 : p 5 2 f u n c t i o n s a s i / o p o r t . 1 : p 5 2 f u n c t i o n s a s o b f 0 o u t p u t p i n . i b f 0 o u t p u t e n a b l e b i t 0 : p 5 3 f u n c t i o n s a s i / o p o r t . 1 : p 5 3 f u n c t i o n s a s i b f 0 o u t p u t p i n . i b f 0 i n t e r r u p t s e l e c t b i t 0 : o c c u r r e n c e d u e t o d a t a w r i t e ( a 0 = 0 ) o r c o m m a n d w r i t e ( a 0 = 1 ) 1 : o c c u r r e n c e d u e t o c o m m a n d w r i t e ( a 0 = 1 ) o u t p u t b u f f e r 0 e m p t y i n t e r r u p t d i s a b l e b i t 0 : e n a b l e d 1 : d i s a b l e d i n p u t b u f f e r 0 f u l l i n t e r r u p t d i s a b l e b i t 0 : e n a b l e d 1 : d i s a b l e d r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) m a s t e r c p u b u s i n t e r f a c e e n a b l e b i t 0 : p 5 4 t o p 5 7 , p 6 0 t o p 6 7 f u n c t i o n a s i / o p o r t s . 1 : p 5 4 t o p 5 7 , p 6 0 t o p 6 7 f u n c t i o n a s m a s t e r c p u b u s i n t e r f a c e f u n c t i o n p i n s . b u s i n t e r f a c e t y p e s e l e c t b i t 0 : r d , w r s e p a r a t e t y p e b u s 1 : r / w t y p e b u s b 0 b7 data bus buffer status register 1 (address 004d 16 ) dbbs1 o u t p u t b u f f e r f u l l f l a g ( o b f 1 ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l i n p u t b u f f e r f u l l f l a g ( i b f 1 ) 0 : b u f f e r e m p t y 1 : b u f f e r f u l l u s e r d e f i n a b l e f l a g ( u 2 ) t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . a 0 f l a g ( a 01 ) t h i s f l a g i n d i c a t e s t h e c o n d i t i o n o f a 0 s t a t u s w h e n t h e i b f 1 f l a g i s s e t . u s e r d e f i n a b l e f l a g ( u 4 C u 7 ) t h i s f l a g c a n b e d e f i n e d b y u s e r f r e e l y . b 0 b 7 o b f 1 o u t p u t e n a b l e b i t 0 : p 7 4 f u n c t i o n s a s i / o p o r t . 1 : p 7 4 f u n c t i o n s a s o b f 1 o u t p u t p i n . i b f 1 o u t p u t e n a b l e b i t 0 : p 7 3 f u n c t i o n s a s p o r t i / o p i n . 1 : p 7 3 f u n c t i o n s a s i b f 1 o u t p u t p i n . i b f 1 i n t e r r u p t s e l e c t b i t 0 : o c c u r r e n c e d u e t o d a t a w r i t e ( a 0 = 0 ) o r c o m m a n d w r i t e ( a 0 = 1 ) 1 : o c c u r r e n c e d u e t o c o m m a n d w r i t e ( a 0 = 1 ) o u t p u t b u f f e r 1 e m p t y i n t e r r u p t d i s a b l e b i t 0 : e n a b l e d 1 : d i s a b l e d i n p u t b u f f e r 1 f u l l i n t e r r u p t d i s a b l e b i t 0 : e n a b l e d 1 : d i s a b l e d r e s e r v e d b i t ( 0 a t r e a d / w r i t e ) d a t a b u s b u f f e r f u n c t i o n s e l e c t b i t 0 : s i n g l e d a t a b u s b u f f e r m o d e ( p 7 2 f u n c t i o n s a s i / o p o r t . ) 1 : d o u b l e d a t a b u s b u f f e r m o d e ( p 7 2 f u n c t i o n s a s s 1 i n p u t p i n . ) b 0 b7 data bus buffer control register 1 (address 004e 16 ) dbbc1 0 00
7641 group rev.4.00 aug 28, 2006 page 61 of 135 rej03b0191-0400 fig. 56 master cpu bus interface block diagram p 6 0 / d q 0 rd wr d b b 1 d b b s t s 0 u 7 u 6 u 5 u 4 a 00 u 2 ibf 0 o b f 0 u 7 u 6 u 5 u 4 a 0 1 u 2 ibf 1 obf 1 p 6 1 / d q 1 p6 2 /dq 2 p6 3 /dq 3 p 6 4 / d q 4 p 6 5 / d q 5 p 6 6 / d q 6 p6 7 /dq 7 p7 2 /s 1 p5 6 /r p 5 7 / w b 7b6b 5 b 4b3b 2b 1b0 r d dbbsts 1 dbb 0 wr p 7 3 / i b f 1 p 7 4 / o b f 1 p 5 2 / o b f 0 p 5 6 / r p 5 7 / w p 5 3 / i b f 0 p 5 5 / a 0 p5 4 /s 0 b 7b6b 5 b 4b3b 2b 1b 0 p 5 5 / a 0 data bus buffer control register 1 (address 004e 16 ) data bus buffer control register 0 (address 004a 16 ) output data bus buffer register 1 ( a d d r e s s 0 0 4 c 1 6 ) input data bus buffer register 1 ( a d d r e s s 0 0 4 c 1 6 ) i np u t d a t a b u s b u f f e r r e g i s t e r 0 ( a d d r e s s 0 0 4 8 1 6 ) output data bus buffer register 0 (address 0048 16 ) s y s t e m b u s i n t e r n a l d a t a b u s
7641 group rev.4.00 aug 28, 2006 page 62 of 135 rej03b0191-0400 [data bus buffer status register 0, 1 (dbbs0, dbbs1)] 0049 16 , 004d 16 the data bus buffer status registers 0, 1 consist of eight bits each. bits 0, 1, and 3 are read-only bits and indicate the status of the data bus buffer. bits 2, 4, 5, 6, and 7 are user definable flags which can be programed, and can be read/written. the host cpu can only read this register when the a 0 pin is set to h . bit 0: output buffer full flag obf 0 , obf 1 when writing data to the output data bus buffer, this flag is set to 1 . when reading the output data bus buffer from the host cpu, this flag is cleared to 0 . bit 1: input buffer full flag ibf 0 , ibf 1 when writing data from the host cpu to the input data bus buffer, this flag is set to 1 . when reading the input data bus buffer from the slave cpu side, this flag is are cleared to 0 . bit 3: a0 flag a 00 , a 01 when writing data from the host cpu to the input data bus buffer, the level of the a 0 pin is latched. [input data bus buffer registers 0, 1 (dbbin 0 , dbbin 1 )] 0048 16 , 004c 16 data on the data bus is latched to dbbin 0 or dbbin 1 by writing request from the host cpu. data of dbbins can be read from the data bus buffer registers (address 0048 16 or 004c 16 ) on the sfr area. [output data bus buffer registers 0, 1 (dbbout 0 , dbbout 1 )] 0048 16 , 004c 16 when writing data to the data bus buffer registers (address 0048 16 or 004c 16 ) on the sfr area, data is set to dbbout 0 or dbbout 1 . data of dbbouts is output onto the data bus by per- forming the reading request from the host cpu when the a 0 pin is set to l .
7641 group rev.4.00 aug 28, 2006 page 63 of 135 rej03b0191-0400 status output signal. obf 0 signal is output. status output signal. ibf 0 signal is output. chip select input. this is used for selecting the data bus buffer, which is selected at l level. address input. this is used for selecting dbbsts and dbbout when the host cpu reads. this is used for distinguishing command from data when the host cpu writes. this is a timing signal for reading data from the data bus buffer to the host cpu. this is a timing signal for writing data to the data bus buffer by the host cpu. chip select input. this is used for selecting the data bus buffer, which is selected at l level. status output signal. ibf 1 signal is output. status output signal. obf 1 signal is output. p5 2 /obf 0 table 8 function description of control i/o pins of master cpu bus interface pin name obf 0 output enable bit ibf 0 output enable bit obf 1 output enable bit input/ output functions obf 0 1 0 00 ibf 1 output enable bit output p5 3 /ibf 0 p5 4 /s 0 p5 5 /a 0 p5 6 /r (e) p5 7 /w (r/w) p7 2 /s 1 p7 3 /ibf 1 /hlda p7 4 /obf 1 ibf 0 s 0 a 0 r (e) w (r/w) s 1 ibf 1 obf 1 0 0 0 1 0 0 0 0 1 0 1 0 output input input input input input output output
7641 group rev.4.00 aug 28, 2006 page 64 of 135 rej03b0191-0400 fig. 57 special count source generator block diagram count source generator the 7641 group has a built-in special count source generator, scsg. this generator consists of two 8-bit timers: scsg1 and scsg2. the output of the special count source generator can be used as a clock source for the timer x, serial i/o and two uarts. scsg operation timers scsg1 and scsg2 are both down count timers. when the count reaches 0 , an underflow occurs at the next count source rising edge and the contents of the corresponding timer latch are loaded to the timer. the division ratio of each scsg-x timer is given by 1 / (n+1), where n is the value set to the scsg-x timer. the output of timer scsg1 is anded with the original clock ( ) to make a count source for timer scsg2. the scsg output is clock scsgclk. the frequency is calculated as follows: scsgclk = ? {n1 / (n1+1)} ? {1 / (n2+1)} n1: value set to scsg1 n2: value set to scsg2 if the scsg1 count stop bit (scsgm1) is set to 1 , or timer scsg1 is set to 0 , the scsg1 count stops. when this happens, the count source for timer scsg2 becomes . data write control when the scsg1 data write control bit or scsg2 data write control bit is set to 0 , and data is written to the scsg-x timer; the data is written to the corresponding latch and timer at the same time. when that bit is set to 1 , the data is only written to the latch. s c s g c l k s c s g 1 c o u n t s t o p b i t s c s g c l k o u t p u t c o n t r o l b i t
7641 group rev.4.00 aug 28, 2006 page 65 of 135 rej03b0191-0400 fig. 58 structure of special count source generator mode register s p e c i a l c o u n t s o u r c e m o d e r e g i s t e r ( a d d r e s s 0 0 2 f 1 6 ) s c s g m s c s g 1 d a t a w r i t e c o n t r o l b i t 0 : w r i t i n g d a t a i n t o b o t h t i m e r l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t i n g d a t a i n t o o n l y t i m e r l a t c h s c s g 1 c o u n t s t o p b i t 0 : c o u n t s t a r t 1 : c o u n t s t o p s c s g 2 d a t a w r i t e c o n t r o l b i t 0 : w r i t i n g d a t a i n t o b o t h t i m e r l a t c h a n d t i m e r s i m u l t a n e o u s l y 1 : w r i t i n g d a t a i n t o o n l y t i m e r l a t c h s c s g c l k o u t p u t c o n t r o l b i t 0 : s c s g c l k o u t p u t d i s a b l e d ( s c s g 1 a n d s c s g 2 c o u n t s s t o p ) 1 : s c s g c l k o u t p u t e n a b l e d r e s e r v e d b i t s ( 0 a t r e a d / w r i t e ) b0 b 7 0 00 0
7641 group rev.4.00 aug 28, 2006 page 66 of 135 rej03b0191-0400 frequency synthesizer (pll) the frequency synthesizer generates the 48 mhz clock required by f usb and f syn , which are multiples of the external input refer- ence f(x in ). figure 59 shows the block diagram for the frequency synthesizer circuit. the frequency synthesizer input bit selects either f(x in ) or f(x cin ) as an input clock f in for the frequency synthesizer. the frequency synthesizer multiply register 2 (fsm2: address 006e 16 ) divides f in to generate f pin , where f pin = f in / 2(n + 1), n: value set to fsm2. when the value of frequency synthesizer multiply register 2 is set to 255, the division is not performed and f pin will equal f in . f vco is generated according to the contents of frequency synthe- sizer multiply register 1 (fsm1: address 006d 16 ), where f vco = f pin ? {2(n + 1)}, n: value set to fsm1. set the value of fsm1 so that the value of f vco is 48 mhz. f syn is generated according to the contents of the frequency syn- thesizer divide register (fsd: address 006f 16 ), where f syn = f vco / 2(m + 1), m: value set to fsd. when the value of the frequency synthesizer divide register is set to 255, the division is not performed and f syn becomes invalid. [frequency synthesizer control register] fsc setting the frequency synthesizer enable bit (fse) to 1 enables the frequency synthesizer. when the frequency synthesizer lock status bit (ls) is 1 in the frequency synthesizer enabled, this in- dicates that f syn and f vco have correct frequencies. make sure to connect a low-pulse filter to the lpf pin when using the frequency synthesizer. in addition, please refer to program- ming notes: frequency synthesizer when recovering from a hardware reset. fsm2 d a t a b u s fsm1 fsc prescaler f in f pin f vco f syn f u s b ( a d d r e s s 0 0 6 e 1 6 ) (address 006d 16 )( a d d r e s s 0 0 6 c 1 6 )( a d d r e s s 0 0 6 f 1 6 ) fsd frequency multiplier frequency divider f r e q u e n c y s y n t h e s i z e r l o c k s t a t u s b i t fig. 59 frequency synthesizer block diagram
7641 group rev.4.00 aug 28, 2006 page 67 of 135 rej03b0191-0400 fig. 60 structure of frequency synthesizer control register f r e q u e n c y s y n t h e s i z e r c o n t r o l r e g i s t e r ( a d d r e s s 0 0 6 c 1 6 ) f s c frequency synthesizer enable bit (fse) 0: disabled 1: enabled fix to 00 . frequency synthesizer input bit (fin) 0: f(x in ) 1: f(x cin ) reserved bit ( 0 at read/write) lpf current control (chg1, chg0) ( note ) b6b5 0 0: not available 0 1: low current 1 0: intermediate current (recommended) 1 1: high current frequency synthesizer lock status bit 0: unlocked 1: locked 0 0 0 n o t e : b i t s 6 a n d 5 a r e s e t t o ( b i t 6 , b i t 5 ) = ( 1 , 1 ) a t r e s e t . w h e n u s i n g t h e f r e q u e n c y s y n t h e s i z e r , w e r e c o m m e n d t o s e t t o ( b i t 6 , b i t 5 ) = ( 1 , 0 ) a f t e r l o c k i n g t h e f r e q u e n c y s y n t h e s i z e r . b 0 b 7
7641 group rev.4.00 aug 28, 2006 page 68 of 135 rej03b0191-0400 reset circuit to reset the microcomputer, reset pin should be held at an l level for 20 cycles or more of . then the reset pin is returned to an h level, and reset is released. they must be performed when the power source voltages are between 3.00 v and 3.60 v or 4.15 v and 5.25 v. after the reset is completed, the program starts from the address contained in address fffa 16 (high-order byte) and address fffb 16 (low-order byte). after oscillation has restarted, the timers 1 and 2 secures waiting time for the internal clock oscillation stabilized automatically by setting the timer 1 to ff 16 and timer 2 to 01 16 . the internal clock retains h level until timer 2 s underflow and it cannot be supplied until the underflow. the pins state during reset are follows: ? when cnvss = h ports p0, p1, p3 3 to p3 7 : outputting pins other than above mentioned ports : inputting ? when cnvss = l all pins : inputting. fig. 62 reset sequence fig. 61 reset circuit example (note) 0.2v cc 0v 0v poweron v cc reset v cc reset power source voltage detection circuit power source voltage reset input voltage note : reset release voltage ; vcc = 3.00 or 4.15 v reset internal reset data address sync x in : 512 clock cycles ? ? ? ? fffa fffb ad h , l ? ? ? ? ad l ad h reset address from the vector table. notes: the question marks (?) indicate an undefined state that depends on the previous state.
7641 group rev.4.00 aug 28, 2006 page 69 of 135 rej03b0191-0400 x : not fixed notes 1: when using the endpoint 1, this contents are 01 16 . (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (32) (33) (34) (35) (36) (37) (38) (39) (40) (41) (42) (43) (44) (45) (46) (47) (48) (49) (50) (51) (52) (53) (54) (55) (56) (57) (58) (59) (60) (61) (62) (63) (64) (65) (66) (67) (68) (69) (70) (71) (72) (73) (74) (75) (76) (77) (78) (79) (80) (81) (82) (83) (84) (85) (86) (87) (88) (89) (90) (91) (92) (93) register contents 0032 16 0033 16 0036 16 0038 16 003a 16 003b 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004c 16 004d 16 004e 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 006a 16 006c 16 006d 16 006e 16 006f 16 ffc916 (ps) (pc h ) (pc l ) address 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 address register contents 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 ff 16 ff 16 ff 16 ff 16 00 16 00 16 00 16 ff 16 ff 16 00 16 00 16 fffb 16 contents fffa 16 contents cpu mode register a (cpua) cpu mode register b (cpub) interrupt request register a (ireqa) interrupt request register b (ireqb) interrupt request register c (ireqc) interrupt control register a (icona) interrupt control register b (iconb) interrupt control register c (iconc) port p0 (p0) port p0 direction register (p0d) port p1 (p1) port p1 direction register (p1d) port p2 (p2) port p2 direction register (p2d) port p3 (p3) port p3 direction register (p3d) port control register (ptc) interrupt polarity select register (ipol) port p2 pull-up control register (pup2) usb control register (usbc) port p6 (p6) port p6 direction register (p6d) port p5 (p5) port p5 direction register (p5d) port p4 (p4) port p4 direction register (p4d) port p7 (p7) port p7 direction register (p7d) port p8 (p8) port p8 direction register (p8d) clock control register (ccr) timer xl (txl) timer xh (txh) timer yl (tyl) timer yh (tyh) timer 1 (t1) timer 2 (t2) timer 3 (t3) timer x mode register (txm) timer y mode register (tym) timer 123 mode register (t123m) serial i/o control register 1 (siocon1) serial i/o control register 2 (siocon2) special count source generator 1 (scsg1) special count source generator 2 (scsg2) special count source mode register (scsgm) uart1 mode register (u1mod) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 1 0 00 0 0 0 uart1 status register (u1sts) uart1 control register (u1con) uart1 rts control register (u1rtsc) uart2 mode register (u2mod) uart2 status register (u2sts) uart2 control register (u2con) uart2 rts control register (u2rtsc) dmac index and status register (dmais) dmac channel x mode register 1 (dmax1) dmac channel x mode register 2 (dmax2) dmac channel x source register low (dmaxsl) dmac channel x source register high (dmaxsh) dmac channel x destination register low (dmaxdl) dmac channel x destination register high (dmaxdh) dmac channel x transfer count register low (dmaxcl) dmac channel x transfer count register high (dmaxch) data bus buffer register 0 (dbb0) data bus buffer status register 0 (dbbs0) data bus buffer control register 0 (dbbc0) data bus buffer register 1 (dbb1) data bus buffer status register 1 (dbbs1) data bus buffer control register 1 (dbbc1) usb address register (usba) usb power management register (usbpm) usb interrupt status register 1 (usbis1) usb interrupt status register 2 (usbis2) usb interrupt enable register 1 (usbie1) usb interrupt enable register 2 (usbie2) usb frame number register low (usbsofl) usb frame number register high (usbsofh) usb endpoint index register (usbindex) usb endpoint x in control register (in_csr) usb endpoint x out control register (out_csr) usb endpoint x in max. packet size register (in_maxp) usb endpoint x out max. packet size register (out_maxp) usb endpoint x out write count register low (wrt_cntl) usb endpoint x out write count register high (wrt_cnth) usb endpoint fifo mode register (usbfifomr) flash memory control register (fmcr) frequency synthesizer control register (fsc) frequency synthesizer multiply register 1 (fsm1) frequency synthesizer multiply register 2 (fsm2) frequency synthesizer divide register (fsm2) rom code protect control register (romcp) processor status register program counter 0 0 0 0 1 1 00 0 1 1 0 0 1 0 0 00 0 0 0 1 1 10 00 0 0 00 1 0 00 0 0 0 1 10 00 0 0 00 1 0 11 0 0 0 1 0 1 0 0 00 0 0 0 1 0 0 00 0 0 0 00 0 0 0 1 0 0 0 0 0 1 0 1 0 1 ?? ??? ?? 0 0 00 0 0 0 1 0 0 00 0 0 0 1 01 (note 1) (note 1) (note 3) (note 3) 3 : the flash memory control register and the rom code protect control register exists in the flash memory version only. 2: since the initial values for other than above mentioned registers and ram contents are indefinite at reset, they must be set. fig. 63 internal status at reset
7641 group rev.4.00 aug 28, 2006 page 70 of 135 rej03b0191-0400 clock generating circuit the 7641 group has two built-in oscillation circuits. an oscillation circuit can be formed by connecting a resonator between x in and x out (x cin and x cout ). use the circuit constants in accordance with the resonator manufacturer s recommended values. no exter- nal resistor is needed between x in and x out since a feed-back resistor exists on-chip. (an external feed-back resistor may be needed depending on conditions.) however, an external feed-back resistor is needed between x cin and x cout . when using an external clock, input the clocks to the x in or x cin pin and leave the x out or x cout pin open. immediately after power on, only the x in oscillation circuit starts oscillating, and x cin and x cout pins function as i/o ports. frequency control the internal system clock can be selected among f syn , f(x in ), f(x in )/2, and f(x cin ). the internal clock is half the frequency of internal system clock. (1) f syn clock this is made by the frequency synthesizer. f(x in ) or f(x cin ) can be selected as its input clock. see also section frequency syn- thesizer . (2) f(x in ) clock the frequency of internal system clock is the frequency of x in pin. (3) f(x in )/2 clock the frequency of internal system clock is half the frequency of x in pin. (4) f(x cin ) clock the frequency of internal system clock is the frequency of x cin pin. if you switch the oscillation between x in - x out and x cin - x cout , stabilize both x in and x cin oscillations. the sufficient time is re- quired for the x cin oscillation to stabilize, especially immediately after power on and at returning from the stop mode. fig. 64 ceramic resonator or quartz-crystal oscillator exter- nal circuit fig. 65 external clock input circuit v cc v ss x cin x cout x in x out open open external oscillation circuit external oscillation circuit v cc v ss x c i n x c o u t x i n x o u t c i n c o u t c c i n c c o u t r f r d n o t e s : i n s e r t a d a m p i n g r e s i s t o r i f r e q u i r e d . t h e r e s i s t a n c e w i l l v a r y d e p e n d i n g o n t h e o s c i l l a t o r a n d t h e o s c i l l a t i o n d r i v e c a p a c i t y s e t t i n g . u s e t h e v a l u e r e c o m m e n d e d b y t h e m a k e r o f t h e o s c i l l a t o r . a l s o , i f t h e o s c i l l a t o r m a n u f a c t u r e r ' s d a t a s h e e t s p e c i f i e s t h a t a f e e d b a c k r e s i s t o r b e a d d e d e x t e r n a l t o t h e c h i p t h o u g h a f e e d b a c k r e s i s t o r e x i s t s o n - c h i p , i n s e r t a f e e d b a c k r e s i s t o r b e t w e e n x i n a n d x o u t f o l l o w i n g t h e i n s t r u c t i o n . r d ( n o t e )
7641 group rev.4.00 aug 28, 2006 page 71 of 135 rej03b0191-0400 (5) low power dissipation mode ? the low power dissipation operation can be realized by stopping the main clock x in when using f(x cin ) as the internal system clock. to stop the main clock, set the main clock (x in -x out ) stop bit of the cpu mode register a to 1 . ? the low power dissipation operation can be realized by disabling the reversed amplifier when inputting external clocks to the x in pin or x cin pin. to disable the reversed amplifier, set the x cout oscillation drive disable bit (ccr5) or x out oscillation drive disable bit (ccr6) of the clock control register to 1 . oscillation control (1) stop mode if the stp instruction is executed, the internal clock stops at h level, and x in and x cin oscillators stop. then the timer 1 is set to ff 16 and the internal clock divided by 8 is automatically se- lected as its count source. additionally, the timer 2 is set to 01 16 and the timer 1 s output is automatically selected as its count source. set the timer 1 and timer 2 interrupt enable bits to disabled ( 0 ) before executing the stp instruction. when using an external in- terrupt to release the stop mode, set the interrupt enable bit to be used to enabled ( 1 ) and the interrupt disable flag (i) to 0 . oscillator restarts at reset or when an external interrupt including usb resume interrupts is received, but the internal clock re- mains at h until the timer 2 underflows. the internal clock is supplied for the first time when the timer 2 underflows. therefore make sure not to set the timer 1 interrupt request bit and timer 2 interrupt request bit to 1 before the stp instruction stops the oscillator. (2) wait mode if the wit instruction is executed, the internal clock stops at h level, but the oscillator does not stop. the internal clock restarts at reset or when an interrupt is received. since the oscillator does not stop, normal operation can be started immediately after the in- ternal clock is restarted. set the interrupt enable bit to be used to release the wait mode to enabled ( 1 ) and the interrupt disable flag (i) to 0 . fig. 66 structure of clock control register clock control register (address 001f 16 ) ccr r e s e r v e d b i t s ( 0 a t r e a d / w r i t e ) f i x t o 0 . x c o u t o s c i l l a t i o n d r i v e d i s a b l e b i t ( c c r 5 ) 0 : x c o u t o s c i l l a t i o n d r i v e i s e n a b l e d . ( w h e n x c i n o s c i l l a t i o n i s e n a b l e d . ) 1 : x c o u t o s c i l l a t i o n d r i v e i s d i s a b l e d . x o u t o s c i l l a t i o n d r i v e d i s a b l e b i t ( c c r 6 ) 0 : x o u t o s c i l l a t i o n d r i v e i s e n a b l e d . ( w h e n x i n o s c i l l a t i o n i s e n a b l e d . ) 1 : x o u t o s c i l l a t i o n d r i v e i s d i s a b l e d . x i n d i v i d e r s e l e c t b i t ( c c r 7 ) v a l i d w h e n c p m a 6 , c p m a 7 = 0 0 0 : f ( x i n ) / 2 i s u s e d f o r t h e s y s t e m c l o c k . 1 : f ( x i n ) i s u s e d f o r t h e s y s t e m c l o c k . b 0 b 7 00000
7641 group rev.4.00 aug 28, 2006 page 72 of 135 rej03b0191-0400 fig. 67 clock generating circuit block diagram w i t i n s t r u c t i o n in t e r n a l c l o c k s t p i n s t r u c t i o n i n t e r r u p t r e q u e s t i n t e r r u p t d i s a b l e f l a g l d r q t p i n 1 d r q t p i n 2 d r q t pin1 d r q t p 2 + rq s dq t pin1 dq t p2+ o s c i l l a t o r c o u n t - d o w n t i m e r 1 t o 2 rq s rq s rq s dq t dq t sq r s qb r delay slow memory wait lpf l p f 1 / 2 frequency synthesizer frequency synthesizer enable bit lpf 1 / 2 p 2 p e r i p h e r a l p 1 p e r i p h e r a l s t p i n s t r u c t i o n stp instruction r e s e t s t p i n s t r u c t i o n p 2 l a t r s t b p 1 h a t r s t b p 2 p e r i p h e r a l p 1 p e r i p h e r a l p 2 o u t p 1 o u t p2latrstb p 1 h a t r s t b p 2 p1 dq t pin2 p2+ m a i n c l o c k ( x i n - x o u t ) s t o p b i t oscstp reset xcoscstp x o s c s t p x d o s c s t p x o d x c d o s c s t p xcod sub-clock (x cin -x cout ) stop bit slow memory wait select bit slow memory wait mode select bit rdy x i n x o u t main clock (x in -x out ) stop bit xoscstp x c i n s u b - c l o c k ( x ci n - x co u t ) s t o p b i t x cout frequency synthesizer input bit f in u s b 4 8 m h z c l o c k o u t p u t f syn f e x t internal system clock select bit f ( x i n ) f ( x ci n ) x in drive select bit p1+, p2+ pin1, pin2 p1hatrstb p2latrstb reset xcoscstp external clock select bit
7641 group rev.4.00 aug 28, 2006 page 73 of 135 rej03b0191-0400 n o t e s rese t c p m a 4 1 0 f s c 0 0 1 x i n c l o c k o s c i l l a t i n g , x c i n c l o c k s t o p p e d , f r e q u e n c y s y n t h e s i z e r c l o c k s t o p p e d , c p m a = 0 c , f s c = 6 0 = f ( x i n / 4 ) 1 : switch the mode by the allows shown between the mode blocks. (do not switch between the modes directly without an allow.) 2 : in stop mode, though the frequency synthesizer is not automatically disabled, the oscillator which sends clocks to the frequenc y synthesizer stops. set the system clock and disable the frequency synthesizer before execution of the stp instruction. 3 : = f(x in )/2 can be also used by setting the x in divider select bit (ccr7) to 1 . then this diagram also applies to that case. 4 : the frequency synthesizer s input can be selected between x in input and x cin input regardless of the system clock. this diagra m assumes the frequency synthesizer s input to be the system clock. enable the oscillator to be used for the frequency synthesizer s inpu t before enabling the frequency synthesizer. 5 : select the x cin input as the frequency synthesizer s input by setting the frequency synthesizer input bit (fsc3) to 1 before stopping x i n oscillation. ( n o t e 3 ) x i n c l o c k o s c i l l a t i n g , x c i n c l o c k s t o p p e d , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = 0 c , f s c = 4 1 = f(x in /4) c p m a 6 0 1 x i n c l o c k o s c i l l a t i n g , x c i n c l o c k s t o p p e d , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = 4 c , f s c = 4 1 = f(pll)/2 (note 3) (note 4) w a i t s t o p ( n o t e 2 ) w a i t f s c 0 0 1 x in clock oscillating, x cin clock oscillating, frequency synthesizer clock stopped, cpma = 1c, fsc = 60 = f ( x i n / 4 ) ( n o t e 3 ) x in clock oscillating, x cin clock oscillating, frequency synthesizer clock oscillating, cpma = 1c, fsc = 41 = f(x in /4) c p m a 6 0 1 x in clock oscillating, x cin clock oscillating, frequency synthesizer clock oscillating, cpma = 5c, fsc = 41 = f(pll)/2 (note 3) (note 4) (note 2) w a i t stop w a i t c p m a 7 1 0 fsc0 0 1 x i n c l o c k o s c i l l a t i n g , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k s t o p p e d , c p m a = 9 c , f s c = 6 0 = f(x cin /2) x i n c l o c k o s c i l l a t i n g , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = 9 c , f s c = 4 1 = f(x cin /2) cpma6 0 1 x i n c l o c k o s c i l l a t i n g , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = d c , f s c = 4 1 = f(pll)/2 (note 4) (note 2) wait s t o p w a i t c p m a 5 1 0 f s c 0 0 1 x i n c l o c k s t o p p e d , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k s t o p p e d , c p m a = b c , f s c = 6 8 = f ( x ci n / 2 ) x i n c l o c k s t o p p e d , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = b c , f s c = 4 9 = f(x cin /2) c p m a 6 0 1 x i n c l o c k s t o p p e d , x c i n c l o c k o s c i l l a t i n g , f r e q u e n c y s y n t h e s i z e r c l o c k o s c i l l a t i n g , c p m a = f c , f s c = 4 9 = f(pll)/2 ( n o t e 2 ) wait s t o p w a i t (note 5) (note 4) remarks : this diagram assumes that: ? stack page is page 1 ? in single-chip mode (depending on the cpu mode register a) ? expresses the internal clock. fig. 68 state transitions of clock
7641 group rev.4.00 aug 28, 2006 page 74 of 135 rej03b0191-0400 processor mode single-chip mode, memory expansion mode, and microprocessor mode which is only in the mask rom version can be selected by using the processor mode bits of cpu mode register a (bits 0 and 1 of address 0000 16 ). in the memory expansion mode and micro- processor mode, a memory can be expanded externally via ports p0 to p3. in these modes, ports p0 to p3 lose their i/o port func- tions and become bus pins. the port direction registers corresponding to those ports become external memory areas. fig. 69 memory maps in processor modes other than single- chip mode (1) single-chip mode select this mode by resetting the mcu with cnv ss connected to v ss . (2) memory expansion mode select this mode by setting the processor mode bits (b1, b0) to 01 in software with cnv ss connected to v ss . this mode enables external memory expansion while maintaining the validity of the in- ternal rom. (3) microprocessor mode select this mode by resetting the mcu with cnv ss connected to v cc , or by setting the processor mode bits (b1, b0) to 10 in soft- ware with cnv ss connected to v ss . in the microprocessor mode, the internal rom is no longer valid and an external memory must be used. do not set this mode in the flash memory version. port name port p0 port p1 port p2 port p3 function outputs low-order 8 bits of address. outputs high-order 8 bits of address. operates as i/o pins for data d 7 to d 0 (including instruction code). p3 0 is the rdy input pin. p3 1 and p3 2 function only as output pins p3 3 is the dma out output pin. p3 4 is the out output pin. p3 5 is the sync out output pin. p3 6 is the wr output pin, and p3 7 is the rd out- put pin. p4 0 is the edma pin. table 9 port functions in memory expansion mode and microprocessor mode port p4 8000 16 0 4 7 0 1 6 0 0 0 0 1 6 f f f f 1 6 0 0 0 8 1 6 0 0 1 0 1 6 i n t e r n a l r a m sfr area 0 0 7 0 1 6 internal rom m 3 7 6 4 1 m 8 s f r a r e a m e m o r y e x p a n s i o n m o d em i c r o p r o c e s s o r m o d e t h e s h a d e d a r e a s a r e e x t e r n a l a r e a s . i n t e r n a l r a m s f r a r e a sfr area 0470 16 0 0 0 0 1 6 f f f f 1 6 0 0 0 8 1 6 0 0 1 0 1 6 0 0 7 0 1 6 8000 16 0 a 7 0 1 6 0000 16 ffff 16 0 0 0 8 1 6 0 0 1 0 1 6 0 0 7 0 1 6 1000 16 reserved area m 3 7 6 4 1 f 8 internal ram i n t e r n a l r o m s f r a r e a m e m o r y e x p a n s i o n m o d e t h e s h a d e d a r e a s a r e e x t e r n a l a r e a s . sfr area
7641 group rev.4.00 aug 28, 2006 page 75 of 135 rej03b0191-0400 fig. 70 structure of cpu mode register a c p u m o d e r e g i s t e r a ( a d d r e s s 0 0 0 0 1 6 ) c p m a processor mode bits b1b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: microprocessor mode ( note 1 ) 1 1: not available stack page select bit 0: page 0 1: page 1 fix to 1 . sub-clock (x cin -x cout ) control bit 0: stopped 1: oscillating main clock (x in -x out ) control bit 0: oscillating 1: stopped internal system clock select bit ( note 2 ) 0: external clock (x in -x out or x cin -x cout ) 1: f syn external clock select bit 0: x in -x out 1: x cin -x cout b 0 b 7 1 n o t e s1 : t h i s i s n o t a v a i l a b l e i n t h e f l a s h m e m o r y v e r s i o n . 2 : w h e n ( c p m a 6 , 7 ) = ( 0 , 0 ) , t h e i n t e r n a l s y s t e m c l o c k c a n b e s e l e c t e d b e t w e e n f ( x i n ) o r f ( x i n ) / 2 b y c c r 7 . t h e i n t e r n a l c l o c k i s t h e i n t e r n a l s y s t e m c l o c k d i v i d e d b y 2 . c p u m o d e r e g i s t e r b ( a d d r e s s 0 0 0 1 1 6 ) c p m b s l o w m e m o r y w a i t s e l e c t b i t s b 1 b 0 0 0 : n o w a i t 0 1 : o n e - t i m e w a i t 1 0 : t w o - t i m e w a i t 1 1 : t h r e e - t i m e w a i t s l o w m e m o r y w a i t m o d e s e l e c t b i t s b 3 b 2 0 0 : s o f t w a r e w a i t 0 1 : n o t a v a i l a b l e 1 0 : r d y w a i t 1 1 : s o f t w a r e w a i t p l u s r d y i n p u t a n y t i m e w a i t e x p a n d e d d a t a m e m o r y a c c e s s b i t 0 : e d m a o u t p u t d i s a b l e d 1 : e d m a o u t p u t e n a b l e d h o l d f u n c t i o n e n a b l e b i t 0 : h o l d f u n c t i o n d i s a b l e d 1 : h o l d f u n c t i o n e n a b l e d r e s e r e v e d b i t ( 0 a t r e a d / w r i t e ) f i x t o 1 . b0 b 7 1 0 fig. 71 structure of cpu mode register b
7641 group rev.4.00 aug 28, 2006 page 76 of 135 rej03b0191-0400 slow memory wait the 7641 group is equipped with the slow memory wait function (software wait, rdy wait, and extended rdy wait: software wait plus rdy input anytime wait) for easier interfacing with external devices that have long access times. the slow memory wait func- tion can be enabled in the memory expansion mode and microprocessor mode. the appropriate wait mode is selected by setting bits 0 to 3 of cpu mode register b (address 0001 16 ). this function can extend the read cycle or write cycle only for access to an external memory. however, this wait function cannot be en- abled for access to addresses 0008 16 to 000f 16 . (1) software wait the software wait is selected by setting 00 to the slow memory wait mode select bits of cpu mode register b (address 0001 16 ). read/write cycles ( l width of rd pin/wr pin) can be extended by one to three cycles. the number of cycles to be extended can be selected with the slow memory wait select bits. when the software wait function is selected, the rdy pin status becomes in- valid. (2) rdy wait rdy wait is selected by setting 10 to the slow memory wait mode select bits of cpu mode register b (address 0001 16 ). when a fixed time of l is input to the rdy pin at the beginning of a read/write cycle (before cycle falls), the mcu goes to the rdy state. the read/write cycle can then be extended by one to three cycles. the number of cycles to be added can be selected by the slow memory wait bits. (3) software wait + extended rdy wait extended rdy wait is selected by setting 11 to the slow memory wait mode select bits of cpu mode register b (address 0001 16 ). the read/write cycle can be extended when a fixed time of l is input to the rdy pin at the beginning of a read/write cycle (before cycle falls). the rdy pin state is checked continually at each fall of cycle until the rdy pin goes to h . when h is in- put to the rdy pin, the wait is released within 1, 2, or 3 cycles (as selected with the slow memory wait bits). fig. 72 software wait timing diagram x in o u t a d o u t rd w r c p m b = 0 0 1 6 c p m b = 0 1 1 6 1-cycle software wait no wait cpmb = 02 16 2-cycle software wait c p m b = 0 3 1 6 3-cycle software wait n o t e : t h i s d i a g r a m a s s u m e s = x i n / 2 . fig. 73 rdy wait timing diagram x in out ad out rd wr cpmb = 08 16 cpmb = 09 16 cpmb = 0a 16 cpmb = 0b 16 rdy t su 1-cycle rdy wait no wait 2-cycle rdy wait 3-cycle rdy wait t su t su t su t su t su note : this diagram assumes = x in /2.
7641 group rev.4.00 aug 28, 2006 page 77 of 135 rej03b0191-0400 fig. 74 extended rdy wait (software wait plus rdy input anytime wait) timing diagram x in out ad out rd wr cpmb = 0c 16 cpmb = 0d 16 cpmb = 0e 16 rdy t su cpmb = 0f 16 cpmb = 0e 16 1-cycle extended rdy wait no wait 2-cycle extended rdy wait t su t su t su t su t su t su t su t su t su t su t su t su x in out ad out rd wr rdy 2-cycle extended rdy wait 3-cycle extended rdy wait t su t su t su t su t su t su t su t su t su t su t su t su t su t su t su note : this diagram assumes = x in /2.
7641 group rev.4.00 aug 28, 2006 page 78 of 135 rej03b0191-0400 hold function the hold function is used for systems that consist of external cir- cuits that access mcu buses without use of the cpu (central processing unit). the hold function is used to generate the tim- ing in which the mcu will relinquish the bus from the cpu to the external circuits. to use the hold function, set the hold function enable bit of cpu mode register b (address 0001 16 ) to 1 . this function can be used with both the hold pin and the hlda pin. the hold signal is a signal from an external circuit requesting the mcu to relinquish use of the bus. when l level is input, the mcu goes to the hold state and remains so while the pin is at l . the oscillator does not stop oscillating during the hold state, there- fore allowing the internal peripheral functions to operate during this time. when the mcu relinquishes use of the bus, l level is output from the hlda pin. the mcu makes ports p0 and p1 (address buses) and port p2 (data bus) tri-state outputs and holds port p3 7 (rd pin) and port p3 6 (wr pin) h level. port p3 4 ( out pin) contin- ues to oscillate. this function is not valid when the mcu is using the ibf 1 function with the hlda pin. expanded data memory access in expanded data memory access mode, the mcu can access a data area larger than 64 kbytes with the lda ($zz), y (indirect y) instruction and the sta ($zz), y (indirect y) instruction. to use this mode, set the expanded data memory access bit of cpu mode register b (address 0001 16 ) to 1 . in this case, port p4 0 (edma pin) goes l level during the read/write cycle of the lda or sta instruction. the determination of which bank to access is done by using an i/ o port to represent expanded addresses exceeding address bus ab 15 . for example, when accessing 4 banks, use two i/o ports to represent address buses ab 16 and ab 17 . fig. 75 hold function timing diagram x i n r d , w r a d d r o u t d a t a i n / o u t h o l d h l d a out tsu(hold- ) th( -hold) t d ( - h l d a l ) t d ( - h l d a h ) n o t e : t h i s d i a g r a m a s s u m e s = x i n / 2 .
7641 group rev.4.00 aug 28, 2006 page 79 of 135 rej03b0191-0400 fig. 76 sta ($ zz), y instruction sequence when edma enabled s y n c o u t r d w r address d a t a p c + 1 pc pc + 2 o p c o d e e d m a b a l bal, 00 b a l + 1 , 0 0 ad l + y, ad h ad l + y, ad h + c a d l ad h i n v a l i dd a t a n e x t o p c o d e s y n c o u t rd w r address d a t a pc +1 pc p c + 2 o p c o d e e d m a bal b a l , 0 0 b a l + 1 , 0 0 ad l + y, ad h ad l + y, ad h + c ad l a d h invalid data n ext op code fig. 77 lda ($ zz), y instruction sequence when edma enabled and t flag = 0 fig. 78 lda ($ zz), y instruction sequence when edma enabled and t flag = 1 s y n c o u t r d w r a d d r e s s d a t a p c + 1 p c x, 00 op code edma bal b a l , 0 0 b a l + 1 , 0 0 ad l + y, ad h ad l + y, ad h + c a d l ad h i n v a l i dd a t a n ext op code pc + 2 i n v a l i dd a t a
7641 group rev.4.00 aug 28, 2006 page 80 of 135 rej03b0191-0400 parameter power source voltage analog power source voltage avcc, ext.cap input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 input voltage reset, x in , x cin input voltage cnv ss mask rom version flash memory version input voltage usb d+, usb d C output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7, x out , x cout, lpf output voltage usb d+, usb d C , ext. cap power dissipation ( note ) operating temperature storage temperature symbol v cc av cc v i v i v i v i v o v o p d t opr t stg electrical characteristics conditions ratings C 0.3 to 6.5 C 0.3 to v cc +0.3 C 0.3 to v cc +0.3 C 0.3 to v cc +0.3 C 0.3 to vcc + 0.3 C 0.3 to 6.5 C 0.5 to 3.8 C 0.3 to v cc +0.3 unit v v v v v v v v all voltages are based on vss. output transistors are cut off. ta = 25 c C 0.5 to 3.8 750 C 20 to 70 C 40 to 125 v mw c c note: the maximum power dissipation depends on the mcu s power dissipation and the specific heat consumption of the package. absolute maximum ratings table 10 absolute maximum ratings
7641 group rev.4.00 aug 28, 2006 page 81 of 135 rej03b0191-0400 table 11 recommended operating conditions (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) power source voltage analog reference voltage power source voltage analog reference voltage h input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h input voltage (selecting vihl level input) p2 0 C p2 7 h input voltage (selecting ttl level input for mbi input) p5 4 C p5 7, p6 0 C p6 7, p7 2 h input voltage reset, x in , x cin , cnvss h input voltage usb d+, usb d C l input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l input voltage (selecting vihl level input) p2 0 C p2 7 l input voltage (selecting ttl level input for mbi input) p5 4 C p5 7, p6 0 C p6 7, p7 2 l input voltage reset, x in , x cin , cnvss l input voltage usb d+, usb d C h total peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l total peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h total average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l total average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 2 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 2 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 3 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 3 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 timer x input frequency ( note 4 ) timer y input frequency ( note 4 ) main clock input frequency ( notes 4, 5 ) sub-clock input frequency ( notes 4, 6 ) v cc avcc v ss av ss v ih v ih v ih v ih v ih v il v il v il v il v il i oh(peak) i ol(peak) i oh(avg) i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) limits v v v v v parameter min. 4.15 4.15 0.8v cc 0.5v cc 2.0 typ. 5.0 5.0 0 0 max. 5.25 v cc symbol unit 0.8v cc 2.0 0 0 0 0 1 32.768 v cc v cc v cc v cc 3.8 0.2v cc 0.16v cc 0.8 0.2v cc 0.8 C 80 80 C 40 40 C 10 10 C 5.0 5.0 5.0 5.0 24 50/5.0 v v v v v v v v v ma ma ma ma ma ma ma ma mhz mhz mhz khz/mhz recommended operating conditions in vcc = 5 v
7641 group rev.4.00 aug 28, 2006 page 82 of 135 rej03b0191-0400 notes 1: the total peak output current is the peak value of the peak currents flowing through all the applicable ports. the total avera ge output current is the average value measured over 100 ms flowing through all the applicable ports. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: the duty of oscillation frequency is 50 %. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins. its maximum oscillation frequency must be 24 mhz. however, make sure to set to 12 mhz or slower. more faster clocks are required as the f(x in ) when using the frequency synthesizer as possible. 6: connect a ceramic resonator or a quartz-crystal oscillator between the x cin and x cout pins. its maximum oscillation frequency must be 50 khz. input an external clock having 5 mhz frequency (max.) from the x cin pin.
7641 group rev.4.00 aug 28, 2006 page 83 of 135 rej03b0191-0400 i oh = C 10 ma h output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h output voltage usb d+, usb d- limits v parameter min. v cc C 2.0 typ. max. symbol unit test conditions v oh v oh table 12 electrical characteristics (1) (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) electrical characteristics in vcc = 5 v usb+, and usb- pins pull-down via a resistor of 15 k ? 5 % usb+ pin pull-up to ext. cap. pin via a resistor of 1.5 k ? 5 % i ol = 10 ma v ol l output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l output voltage usb d+, usb d- usb+, and usb- pins pull-down via a resistor of 15 k ? 5 % usb+ pin pull-up to ext. cap. pin via a resistor of 1.5 k ? 5 % v t+ C v t- hysteresis cntr 0 , cntr 1 , int 0 , int 1 , rdy, hold, p2 0 C p2 7 hysteresis urxd1, urxd2 (sclk), cts 2 (srxd), srdy, cts 1 hysteresis reset h input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h input current reset, cnv ss h input current x in h input current x cin l input current p0 0 C p0 7 , p1 0 C p1 7 , p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l input current reset l input current cnv ss l input current x in l input current x cin l input current p2 0 C p2 7 v t+ C v t- v t+ C v t- i ih i ih i ih i ih i il i il i il i il i il i il v i = v cc v i = v ss v i = v ss pull-ups off v cc = 5.0 v, v i = v ss pull-ups on when clock is stopped 2.8 C 30 2.0 0.5 0.5 0.5 9.0 C 9.0 C 65 3.6 2.0 0.3 5.0 5.0 20 5.0 C 5.0 C 5.0 C 20 C 20 C 5.0 C 5.0 v v v v v v a a a a a a a a a a a v ol C 140 5.25 v v ram
7641 group rev.4.00 aug 28, 2006 page 84 of 135 rej03b0191-0400 power source current (output transistor is isolated.) limits parameter min. typ. 40 max. 90 symbol unit test conditions i cc ma table 13 electrical characteristics (2) (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) in vcc = 5 v normal mode ( note 1 ) f(x in ) = 24 mhz, = 12 mhz usb operating frequency synthesizer on wait mode ( note 2 ) f(x in ) = 24 mhz, = 12 mhz usb block enabled, usb clock stopped, frequency synthesizer on wait mode ( note 3 ) f(x cin ) = 32 khz, = 16 khz usb block disabled frequency synthesizer off usb transceiver dc-dc converter off stop mode usb transceiver dc-dc converter on low current mode (usbc3 = 1 ) stop mode usb transceiver dc-dc converter off ta = 25 c stop mode usb transceiver dc-dc converter off ta = 70 c 5.0 100 11 10 250 1.0 10 ma a a a a notes 1: operating in single-chip mode clock input from x in pin (x out oscillator stopped) usb operating with usb transceiver dc-dc converter enabled operating functions: frequency synthesizer, cpu, two uarts, dmac, timers and count source generator disabled functions: master cpu bus interface and serial i/o 2: operating in single-chip mode with wait mode clock input from x in pin (x out oscillator stopped) usb suspended due to usb clock stopped with usb transceiver dc-dc converter enabled operating functions: frequency synthesizer, timers and count source generator disabled functions: cpu, two uarts, dmac, master cpu bus interface and serial i/o 3: operating in single-chip mode with wait mode x in - x out oscillator stopped clock input from x cin pin (x cout oscillator stopped) usb stopped, usb clock stopped and usb transceiver dc-dc converter disabled operating functions: timers and count source generator disabled functions: frequency synthesizer, cpu, two uarts, dmac, master cpu bus interface and serial i/o
7641 group rev.4.00 aug 28, 2006 page 85 of 135 rej03b0191-0400 reset input l pulse width main clock input cycle time ( note ) main clock input h pulse width main clock input l pulse width sub-clock input cycle time sub-clock input h pulse width sub-clock input l pulse width int 0 , int 1 input cycle time int 0 , int 1 input h pulse width int 0 , int 1 input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width timer t out delay time timer cntr 0 delay time (pulse output mode) timer cntr 0 input cycle time (event counter mode) timer cntr 0 input h pulse width (event counter mode) timer cntr 0 input l pulse width (event counter mode) timer cntr 1 delay time (pulse output mode) timer cntr 1 input cycle time (event counter mode) timer cntr 1 input h pulse width (event counter mode) timer cntr 1 input l pulse width (event counter mode) serial i/o external clock input cycle time serial i/o external clock input h pulse width serial i/o external clock input l pulse width serial i/o input setup time (external clock) serial i/o input hold time (external clock) serial i/o output delay time (external clock) serial i/o srdy valid time (external clock) serial i/o internal clock output cycle time serial i/o internal clock output h pulse width serial i/o internal clock output l pulse width serial i/o input setup time (internal clock) serial i/o input hold time (internal clock) serial i/o output delay time (internal clock) t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (int) t wh (int) t wl (int) t c (cntri) t wh (cntri) t wl (cntri) t d ( -tout) t d ( -cntr 0 ) t c (cntr e0 ) t wh (cntr e0 ) t wl (cntr e0 ) t d ( -cntr 1 ) t c (cntr e1 ) t wh (cntr e1 ) t wl (cntr e1 ) t c (sclk e ) t wh (sclk e ) t wl (sclk e ) t su (srxd-sclk e ) t h (sclk e -srxd) t d (sclk e -stxd) t v (sclk e -srdy) t c (sclk i ) t wh (sclk i ) t wl (sclk i ) t su (srxd-sclk i ) t h (sclk i -srxd) t d (sclk i -stxd) limits s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 41.66 0.4 ? tc(x in ) 0.4 ? tc(x in ) 200 0.4 ? tc(x cin ) 0.4 ? tc(x cin ) 200 90 90 200 80 80 200 0.4 ? tc(cntr e0 ) 0.4 ? tc(cntr e0 ) 200 0.4 ? tc(cntr e1 ) 0.4 ? tc(cntr e1 ) 400 190 180 15 10 166.66 0.5 ? tc(sclk i ) C 5 0.5 ? tc(sclk i ) C 5 20 5 typ. max. symbol unit table 14 timing requirements (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) note: make sure not to exceed 12 mhz of , in other words, tc( ) 83.33 ns). for example, set bit 7 of the clock control register (ccr) to 0 in the case of tc(x in ) < 41.66 ns. timing requirements in vcc = 5 v 15 15 15 25 26 5
7641 group rev.4.00 aug 28, 2006 page 86 of 135 rej03b0191-0400 s 0 , s 1 setup time for read s 0 , s 1 setup time for write s 0 , s 1 hold time for read s 0 , s 1 hold time for write a 0 setup time for read a 0 setup time for write a 0 hold time for read a 0 hold time for write read pulse width write pulse width data input setup time before write data input hold time after write data output enable time after read data output disable time after read obf output transmission time after read ibf output transmission time after write t su (s-r) t su (s-w) t h (r-s) t h (w-s) t su (a-r) t su (a-w) t h (r-a) t h (w-a) t w (r) t w (w) t su (d-w) t h (w-d) ta (r-d) tv (r-d) tv (r-obf) td (w-ibf) limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 0 0 10 10 0 0 50 50 25 0 10 typ. max. symbol unit table 15 master cpu bus interface (mbi; rd, wr separate type) (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) in vcc = 5 v 40 40 40 s 0 , s 1 setup time s 0 , s 1 hold time a 0 setup time a 0 hold time r/w setup time r/w hold time enable pulse width enable pulse interval data input setup time before write data input hold time after write data output enable time after read data output disable time after read obf output transmission time after e inactive ibf output transmission time after e inactive t su (s-e) t h( e-s) t su (a-e) t h (e-a) t su (rw-e) t h (e-rw) t w (e) t w (e-e) t su (d-e) t h (e-d) t a (e-d) t v (e-d) t v (e-obf) t d (e-ibf) limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 10 0 10 10 50 50 25 0 10 typ. max. symbol unit table 16 master cpu bus interface (mbi; r/w type) (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) 40 40 40 in vcc = 5 v
7641 group rev.4.00 aug 28, 2006 page 87 of 135 rej03b0191-0400 clock cycle time clock h pulse width clock l pulse width ab 15 C ab 8 delay time ab 15 C ab 8 valid time ab 7 C ab 0 delay time ab 7 C ab 0 valid time wr delay time wr valid time rd delay time rd valid time sync out delay time sync out valid time dma out delay time dma out valid time rdy setup time rdy hold time hold setup time hold hold time hold l delay time hold h delay time data bus setup time data bus hold time data bus delay time data bus valid time ( note 1 ) edma delay time edma valid time wr pulse width rd pulse width ab 15 C ab 8 valid time before wr ab 7 C ab 0 valid time before wr ab 15 C ab 8 valid time after wr ab 7 C ab 0 valid time after wr ab 15 C ab 8 valid time before rd ab 7 C ab 0 valid time before rd ab 15 C ab 8 valid time after rd ab 7 C ab 0 valid time after rd rdy setup time before wr rdy hold time after wr rdy setup time before rd rdy hold time after rd data bus setup time before rd data bus hold time after rd data bus delay time before wr data bus valid time after wr ( note 1 ) edma delay time after wr edma valid time after rd usb output rise time, c l = 50 pf usb output fall time, c l = 50 pf t c ( ) t wh ( ) t wl ( ) t d ( -ah) t v ( -ah) t d ( -al) t v ( -al) t d ( -wr) t v ( -wr) t d ( -rd) t v ( -rd) t d ( -sync) t v ( -sync) t d ( -dma) t v ( -dma) t su (rdy- ) t h ( -rdy) t su (hold- ) t h ( -hold) t d ( -hldal) t d ( -hldah) t su (db- ) t h ( -db) t d ( -db) t v ( -db) t d ( -edma) t v ( -edma) t wl (wr) ( note 2 ) t wl (rd) ( note 2 ) t d (ah-wr) t d (al-wr) t v (wr-ah) t v (wr-al) t d (ah-rd) t d (al-rd) t v (rd-ah) t v (rd-al) t su (rdy-wr) t h (wr-rdy) t su (rdy-rd) t h (rd-rdy) t su (db-rd) t h (rd-db) t d (wr-db) t v (wr-db) t v (wr-edma) t v (rd-edma) t r (d+), t r (d-) t f (d+), t f (d-) limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 83.33 0.5 ? tc( ) C 5 0.5 ? tc( ) C 5 5 5 3 3 4 5 21 0 21 0 7 0 13 4 0.5 ? tc( ) C 5 0.5 ? tc( ) C 5 0.5 ? tc( ) C 28 0.5 ? tc( ) C 30 0 0 0.5 ? tc( ) C 28 0.5 ? tc( ) C 30 0 0 27 0 27 0 13 0 10 2 2 4 4 typ. max. symbol unit table 17 timing requirements and switching characteristics in memory expansion and microprocessor modes (vcc = 4.15 to 5.25 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) 31 33 6 6 6 25 in vcc = 5 v 25 25 22 9 20 20 20
7641 group rev.4.00 aug 28, 2006 page 88 of 135 rej03b0191-0400 notes 1: test conditions: i ohl = 5ma, c l = 50 pf 2: t wl (rd) = ((n + 0.5) ? tc(phi)) C 5 ns (n = wait number) t wl (wr) = ((n + 0.5) ? tc(phi)) C 5 ns (n = wait number) for example, two software waits, phi = 12 mhz operating t wl (rd) = 2.5 ? tc(phi) C 5 ns = 203.33 ns table 18 recommended operating conditions (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) power source voltage analog reference voltage power source voltage analog reference voltage dc-dc converter voltage h input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h input voltage (selecting vihl level input) p2 0 C p2 7 h input voltage reset, x in , x cin , cnvss h input voltage usb d+, usb d C l input voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l input voltage (selecting vihl level input) p2 0 C p2 7 l input voltage reset, x in , x cin , cnvss l input voltage usb d+, usb d C h total peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l total peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h total average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l total average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 1 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 2 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l peak output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 2 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 3 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l average output current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, ( note 3 )p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 timer x input frequency ( note 4 ) timer y input frequency ( note 4 ) main clock input frequency ( notes 4, 5 ) sub-clock input frequency ( notes 4, 6 ) v cc avcc v ss av ss ext. cap. v ih v ih v ih v ih v il v il v il v il i oh(peak) i ol(peak) i oh(avg) i ol(avg) i oh(peak) i ol(peak) i oh(avg) i ol(avg) f(cntr 0 ) f(cntr 1 ) f(x in ) f(x cin ) limits v v v v v parameter min. 3.0 3.0 3.0 0.8v cc 0.5v cc 0.8v cc 2.0 0 typ. 3.3 3.3 0 0 3.3 max. 3.6 v cc symbol unit 3.6 v cc recommended operating conditions in vcc = 3 v 0 0 1 v cc v cc 0.2v cc 0.16v cc 0.2v cc 0.8 C 80 80 C 40 40 C 10 10 C 5.0 v v v v v v v v ma ma ma ma ma ma ma ma ma 32.768 5.0 5.0 5.0 24 50/5.0 mhz mhz mhz khz/mhz
7641 group rev.4.00 aug 28, 2006 page 89 of 135 rej03b0191-0400 notes 1: the total peak output current is the peak value of the peak currents flowing through all the applicable ports. the total avera ge output current is the average value measured over 100 ms flowing through all the applicable ports. 2: the peak output current is the peak current flowing in each port. 3: the average output current is an average value measured over 100 ms. 4: the duty of oscillation frequency is 50 %. connect a ceramic resonator or a quartz-crystal oscillator between the x in and x out pins. its maximum oscillation frequency must be 24 mhz. however, make sure to set to 6 mhz or slower. more faster clocks are required as the f(x in ) when using the frequency synthesizer as possible. 6: connect a ceramic resonator or a quartz-crystal oscillator between the x cin and x cout pins. its maximum oscillation frequency must be 50 khz. input an external clock having 5 mhz (max.) frequency from the x cin pin.
7641 group rev.4.00 aug 28, 2006 page 90 of 135 rej03b0191-0400 table 19 electrical characteristics (1) (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) electrical characteristics in vcc = 3 v i oh = C 1 ma h output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h output voltage usb d+, usb d- limits v parameter min. v cc C 1.0 typ. max. symbol unit test conditions v oh v oh usb+, and usb- pins pull-down via a resistor of 15 k ? 5 % usb+ pin pull-up to ext. cap. pin via a resistor of 1.5 k ? 5 % i ol = 1 ma v ol l output voltage p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l output voltage usb d+, usb d- usb+, and usb- pins pull-down via a resistor of 15 k ? 5 % usb+ pin pull-up to ext. cap. pin via a resistor of 1.5 k ? 5 % v t+ C v t- hysteresis cntr 0 , cntr 1 , int 0 , int 1 , rdy, hold, p2 0 C p2 7 hysteresis urxd1, urxd2 (sclk), cts 2 (srxd), srdy, cts 1 hysteresis reset h input current p0 0 C p0 7 , p1 0 C p1 7 , p2 0 C p2 7, p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 h input current reset, cnv ss h input current x in h input current x cin l input current p0 0 C p0 7 , p1 0 C p1 7 , p3 0 C p3 7, p4 0 C p4 4, p5 0 C p5 7, p6 0 C p6 7, p7 0 C p7 4, p8 0 C p8 7 l input current reset l input current cnv ss l input current x in l input current x cin l input current p2 0 C p2 7 v t+ C v t- v t+ C v t- i ih i ih i ih i ih i il i il i il i il i il i il v i = v cc v i = v ss v i = v ss pull-ups off v cc = 3.0 v, v i = v ss pull-ups on when clock is stopped 2.8 C 10 2.0 0.3 0.3 0.3 9.0 C 9.0 C 20 3.6 1.0 0.3 5.0 5.0 20 5.0 C 5.0 C 5.0 C 20 C 20 C 5.0 C 5.0 v v v v v v a a a a a a a a a a a v ol C 50 v v ram 0
7641 group rev.4.00 aug 28, 2006 page 91 of 135 rej03b0191-0400 table 20 electrical characteristics (2) (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) in vcc = 3 v power source current (output transistor is isolated.) limits parameter min. typ. 25 max. 45 symbol unit test conditions i cc ma normal mode ( note 1 ) f(x in ) = 24 mhz, = 6 mhz usb operating frequency synthesizer on wait mode ( note 2 ) f(x in ) = 24 mhz, = 6 mhz usb block enabled, usb clock stopped, frequency synthesizer on wait mode ( note 3 ) f(x cin ) = 32 khz, = 16 khz usb block disabled frequency synthesizer off usb transceiver dc-dc converter off stop mode usb transceiver dc-dc converter off ta = 25 c stop mode usb transceiver dc-dc converter off ta = 70 c 2.5 6 6 1.0 10 ma a a a notes 1: operating in single-chip mode clock input from x in pin (x out oscillator stopped) usb operating with usb transceiver dc-dc converter enabled operating functions: frequency synthesizer, cpu, two uarts, dmac, timers and count source generator disabled functions: master cpu bus interface and serial i/o 2: operating in single-chip mode with wait mode clock input from x in pin (x out oscillator stopped) usb suspended due to usb clock stopped with usb transceiver dc-dc converter enabled operating functions: frequency synthesizer, timers and count source generator disabled functions: cpu, two uarts, dmac, master cpu bus interface and serial i/o 3: operating in single-chip mode with wait mode x in - x out oscillator stopped clock input from x cin pin (x cout oscillator stopped) usb stopped, usb clock stopped and usb transceiver dc-dc converter disabled operating functions: timers and count source generator disabled functions: frequency synthesizer, cpu, two uarts, dmac, master cpu bus interface and serial i/o
7641 group rev.4.00 aug 28, 2006 page 92 of 135 rej03b0191-0400 reset input l pulse width main clock input cycle time ( note ) main clock input h pulse width main clock input l pulse width sub-clock input cycle time sub-clock input h pulse width sub-clock input l pulse width int 0 , int 1 input cycle time int 0 , int 1 input h pulse width int 0 , int 1 input l pulse width cntr 0 , cntr 1 input cycle time cntr 0 , cntr 1 input h pulse width cntr 0 , cntr 1 input l pulse width timer t out delay time timer cntr 0 delay time (pulse output mode) timer cntr 0 input cycle time (event counter mode) timer cntr 0 input h pulse width (event counter mode) timer cntr 0 input l pulse width (event counter mode) timer cntr 1 delay time (pulse output mode) timer cntr 1 input cycle time (event counter mode) timer cntr 1 input h pulse width (event counter mode) timer cntr 1 input l pulse width (event counter mode) serial i/o external clock input cycle time serial i/o external clock input h pulse width serial i/o external clock input l pulse width serial i/o input setup time (external clock) serial i/o input hold time (external clock) serial i/o output delay time (external clock) serial i/o srdy valid time (external clock) serial i/o internal clock output cycle time serial i/o internal clock output h pulse width serial i/o internal clock output l pulse width serial i/o input setup time (internal clock) serial i/o input hold time (internal clock) serial i/o output delay time (internal clock) t w (reset) t c (x in ) t wh (x in ) t wl (x in ) t c (x cin ) t wh (x cin ) t wl (x cin ) t c (int) t wh (int) t wl (int) t c (cntri) t wh (cntri) t wl (cntri) t d ( -tout) t d ( -cntr 0 ) t c (cntr e0 ) t wh (cntr e0 ) t wl (cntr e0 ) t d ( -cntr 1 ) t c (cntr e1 ) t wh (cntr e1 ) t wl (cntr e1 ) t c (sclk e ) t wh (sclk e ) t wl (sclk e ) t su (srxd-sclk e ) t h (sclk e -srxd) t d (sclk e -stxd) t v (sclk e -srdy) t c (sclk i ) t wh (sclk i ) t wl (sclk i ) t su (srxd-sclk i ) t h (sclk i -srxd) t d (sclk i -stxd) limits s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 2 41.66 0.4 ? tc(x in ) 0.4 ? tc(x in ) 200 0.4 ? tc(x cin ) 0.4 ? tc(x cin ) 250 110 110 250 110 110 250 0.4 ? tc(cntr e0 ) 0.4 ? tc(cntr e0 ) 250 0.4 ? tc(cntr e1 ) 0.4 ? tc(cntr e1 ) 450 220 190 20 15 300 0.5 ? tc(sclk i ) C 5 0.5 ? tc(sclk i ) C 5 20 5 typ. max. symbol unit table 21 timing requirements (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) note: make sure not to exceed 6 mhz of , in other words, tc( ) 166.66 ns). timing requirements in vcc = 3 v 17 16 15 34 35 5
7641 group rev.4.00 aug 28, 2006 page 93 of 135 rej03b0191-0400 s 0 , s 1 setup time for read s 0 , s 1 setup time for write s 0 , s 1 hold time for read s 0 , s 1 hold time for write a 0 setup time for read a 0 setup time for write a 0 hold time for read a 0 hold time for write read pulse width write pulse width data input setup time before write data input hold time after write data output enable time after read data output disable time after read obf output transmission time after read ibf output transmission time after write t su (s-r) t su (s-w) t h (r-s) t h (w-s) t su (a-r) t su (a-w) t h (r-a) t h (w-a) t w (r) t w (w) t su (d-w) t h (w-d) ta (r-d) tv (r-d) tv (r-obf) td (w-ibf) limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 0 0 10 10 0 0 80 80 35 0 10 typ. max. symbol unit table 22 master cpu bus interface (mbi; rd, wr separate type) (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) in vcc = 3 v 65 50 50 s 0 , s 1 setup time s 0 , s 1 hold time a 0 setup time a 0 hold time r/w setup time r/w hold time enable pulse width enable pulse interval data input setup time before write data input hold time after write data output enable time after read data output disable time after read obf output transmission time after e inactive ibf output transmission time after e inactive t su (s-e) t h( e-s) t su (a-e) t h (e-a) t su (rw-e) t h (e-rw) t w (e) t w (e-e) t su (d-e) t h (e-d) t a (e-d) t v (e-d) t v (e-obf) t d (e-ibf) limits ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 0 0 10 0 10 10 80 80 35 0 10 typ. max. symbol unit table 23 master cpu bus interface (mbi; r/w type) (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) 65 50 50 in vcc = 3 v
7641 group rev.4.00 aug 28, 2006 page 94 of 135 rej03b0191-0400 clock cycle time clock h pulse width clock l pulse width ab 15 C ab 8 delay time ab 15 C ab 8 valid time ab 7 C ab 0 delay time ab 7 C ab 0 valid time wr delay time wr valid time rd delay time rd valid time sync out delay time sync out valid time dma out delay time dma out valid time rdy setup time rdy hold time hold setup time hold hold time hold l delay time hold h delay time data bus setup time data bus hold time data bus delay time data bus valid time ( note 1 ) edma delay time edma valid time wr pulse width rd pulse width ab 15 C ab 8 valid time before wr ab 7 C ab 0 valid time before wr ab 15 C ab 8 valid time after wr ab 7 C ab 0 valid time after wr ab 15 C ab 8 valid time before rd ab 7 C ab 0 valid time before rd ab 15 C ab 8 valid time after rd ab 7 C ab 0 valid time after rd rdy setup time before wr rdy hold time after wr rdy setup time before rd rdy hold time after rd data bus setup time before rd data bus hold time after rd data bus delay time after wr data bus valid time after wr ( note 1 ) edma delay time after wr edma valid time after rd usb output rise time, c l = 50 pf usb output fall time, c l = 50 pf t c ( ) t wh ( ) t wl ( ) t d ( -ah) t v ( -ah) t d ( -al) t v ( -al) t d ( -wr) t v ( -wr) t d ( -rd) t v ( -rd) t d ( -sync) t v ( -sync) t d ( -dma) t v ( -dma) t su (rdy- ) t h ( -rdy) t su (hold- ) t h ( -hold) t d ( -hldal) t d ( -hldah) t su (db- ) t h ( -db) t d ( -db) t v ( -db) t d ( -edma) t v ( -edma) t wl (wr) ( note 2 ) t wl (rd) ( note 2 ) t d (ah-wr) t d (al-wr) t v (wr-ah) t v (wr-al) t d (ah-rd) t d (al-rd) t v (rd-ah) t v (rd-al) t su (rdy-wr) t h (wr-rdy) t su (rdy-rd) t h (rd-rdy) t su (db-rd) t h (rd-db) t d (wr-db) t v (wr-db) t v (wr-edma) t v (rd-edma) t r (d+), t r (d-) t f (d+), t f (d-) limits s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns parameter min. 166.66 0.5 ? tc( ) C 5 0.5 ? tc( ) C 5 7 7 4 3 4 9 35 0 21 0 9 0 15 8 0.5 ? tc( ) C 6 0.5 ? tc( ) C 6 0.5 ? tc( ) C 33 0.5 ? tc( ) C 35 0 0 0.5 ? tc( ) C 33 0.5 ? tc( ) C 35 0 0 45 0 45 0 18 0 12 3 3 4 4 typ. max. symbol unit table 24 timing requirements and switching characteristics in memory expansion and microprocessor modes (vcc = 3.0 to 3.6 v, vss = 0 v, ta = C 20 to 70 c, unless otherwise noted) 45 47 8 8 11 26 in vcc = 3 v 30 30 30 12 28 20 20
7641 group rev.4.00 aug 28, 2006 page 95 of 135 rej03b0191-0400 fig. 79 circuit for measuring output switching characteristics (1) notes 1: test conditions: i ohl = 5ma, c l = 50 pf 2: t wl (rd) = ((n + 0.5) ? tc(phi)) C 5 ns (n = wait number) t wl (wr) = ((n + 0.5) ? tc(phi)) C 5 ns (n = wait number) for example, two software waits, phi = 12 mhz operating t wl (rd) = 2.5 ? tc(phi) C 5 ns = 203.33 ns measurement output pin 100 pf cmos output n -c h anne l open- d ra i n output ( n ote ) 1 k ? 1 0 0 p f m easurement output p i n n ote : thi s di agram app li es w h en bi t 7 o f t h e ser i a l i / o contro l register 1 is 1 . fig. 80 circuit for measuring output switching characteristics (2)
7641 group rev.4.00 aug 28, 2006 page 96 of 135 rej03b0191-0400 0.2v cc t wl(int) 0.8v cc t wh(int) 0.5v cc 0.2v cc t wl(x in ) 0.8v cc t wh(x in ) t c(x in ) x in 0.2v cc 0.8v cc t w(reset) reset t d( C t out ) t out int 0, int 1 0.2v cc t wl(cntr i ) 0.8v cc t wh(cntr i ) t c(cntr i ) cntr 0 , cntr 1 0.2v cc t wl(x cin ) 0.8v cc t wh(x cin ) t c(x cin ) x cin t d( C cntr 0 , 1 ) 0.2v cc t wl(cntr e0 , 1 ) 0.8v cc t wh(cntr e0 , 1 ) t c(cntr e0 , 1 ) cntr 0 , cntr 1 cntr 0 , cntr 1 0.5v cc 0.5v cc t c(int) timing diagram [interrupt] [input] [timer]
7641 group rev.4.00 aug 28, 2006 page 97 of 135 rej03b0191-0400 0.2v cc 0.2v cc 0.8v cc 0.8v cc t d(sclk e, i C stxd) t c(sclk e,i ) t wl(sclk e, i ) t wh(sclk e,i ) th(sclk e, i C srxd) t su(srxd C sclk e, i ) stxd srxd sclk srdy t v(sclk e C srdy) 0.5v cc 0.8v cc timing diagram [serial i/o] fig. 82 timing diagram (2) tf( d +) tf( d -) tr( d +) tr( d -) usbd+, usbd- 0.1v oh 0.9v oh fig. 83 timing diagram (3)
7641 group rev.4.00 aug 28, 2006 page 98 of 135 rej03b0191-0400 0 . 8 v c c 0 . 2 v c c dq 0 to dq 7 r s 0, s 1 a 0 t su(a-r) 0.8v cc (2.0v) 0.2v cc (0.8v) t h(r-a) 0 . 2 v c c ( 0 . 8 v ) t h ( r - s ) t su(s-r) 0.8v cc (2.0v) 0.2v cc (0.8v) t w ( r ) 0.8v cc 0.2v cc t a(r-d) t v ( r - d ) o b f 0.2v cc t v(r-obf) 0.8v cc 0.2v cc d q 0 t o d q 7 w s 0, s 1 a 0 t s u ( a - w ) 0.8v cc (2.0v) 0.2v cc (0.8v) t h(w-a) 0.2v cc (0.8v) t h ( w - s ) t su(s-w) 0.8v cc (2.0v) 0.2v cc (0.8v) t w ( w ) 0.8v cc 0.2v cc t h(w-d) i b f 0 . 2 v c c t d(w-ibf) t su(d-w) t i m i n g d i a g r a m [ m a s t e r c p u b u s i n t e r f a c e : r / w s e p a r a t e m o d e ] < r e a d > < w r i t e > n o t e : t h i s t i m i n g a p p l i e s i n t h e c a s e o f t h e m a s t e r b u s i n p u t l e v e l s e l e c t b i t ( p t c 7 ) = 1 ( t t l l e v e l i n p u t ) fig. 84 timing diagram (4)
7641 group rev.4.00 aug 28, 2006 page 99 of 135 rej03b0191-0400 t su(a-e) s 0, s 1 a 0 r / w 0 . 8 v c c ( 2 . 0 v ) 0 . 2 v c c ( 0 . 8 v ) t h ( e - a ) 0 . 2 v c c ( 0 . 8 v ) t h ( e - s ) t su(s-e) obf, ibf 0 . 2 v c c t v(e-obf) t d(e-ibf) e 0.2v cc (0.8v) 0 . 8 v c c ( 2 . 0 v ) 0 . 2 v c c ( 0 . 8 v ) t w ( e - e ) t w ( e ) 0.8v cc 0.2v cc dq 0 to dq 7 0.8v cc 0.2v cc t a(e-d) t v(e-d) 0 . 8 v c c 0 . 2 v c c d q 0 t o d q 7 0.8v cc 0.2v cc t h ( e - d ) t su(d-e) t i m i n g d i a g r a m [ m a s t e r c p u b u s i n t e r f a c e : r / w m o d e ] < w r i t e > note : this timing applies in the case of the master bus input level select bit (ptc7) = 1 (ttl level input) < r e a d > fig. 85 timing diagram (5)
7641 group rev.4.00 aug 28, 2006 page 100 of 135 rej03b0191-0400 t wl( ) 0.5v cc t wh( ) t c( ) t d( -ah) t d( -al) t d( -sync) t v( -ah) t v( -al) t v( -sync) t d( -wr) t d( -rd) t v( -wr) t v( -rd) 0.5v cc 0.5v cc 0.5v cc ab 15 to ab 8 ab 7 to ab 0 sync out rd,wr dma out 0.8v cc 0.2v cc t h( -db) 0.5v cc t d( -db) t v( -db) db 0 to db 7 db 0 to db 7 0.5v cc t v( -dma) 0.5v cc t d( -dma) rdy 0.8v cc 0.2v cc t su(rdy- ) t h( -rdy) hold (at entering) 0.8v cc 0.2v cc t su(hold- ) t h( -hold) hlda t d( -hldal) hold (at releasing) 0.8v cc 0.2v cc t su(hold- ) t h( -hold) hlda t d( -hldah) 0.5v cc 0.5v cc t su(db- ) edma 0.5v cc t v( -edma) 0.5v cc t d( -edma) n cycles of
7641 group rev.4.00 aug 28, 2006 page 101 of 135 rej03b0191-0400 0.5v cc rd,wr 0.5v cc ab 15 to ab 8 t d(ah-wr) t v(wr-ah) 0.5v cc ab 7 to ab 0 t d(al-wr) t v(wr-al) 0.8v cc 0.2v cc db 0 to db 7 t su(db-rd) t h(rd-db) 0.5v cc db 0 to db 7 t d(wr-db) t v(wr-db) rdy t v(rd-ah) t d(ah-rd) t d(al-rd) t v(rd-al) t wl(rd) t wl(wr) 0.8v cc 0.2v cc t su(rdy-wr) tsu(rdy-rd) t h(wr-rdy) th(rd-rdy) edma 0.5v cc t v(wr-edma) t v(rd-edma) fig. 87 timing diagram (7); memory expansion and microprocessor modes
7641 group rev.4.00 aug 28, 2006 page 102 of 135 rej03b0191-0400 table 25 summary of m37641f8 (flash memory version) flash memory mode the m37641f8fp/hp (flash memory version) has an internal new dinor (divided bit line nor) flash memory that can be rewritten with a single power source when v cc is 5 v, and 2 power sources when v pp is 5 v and v cc is 3.3 v in the cpu rewrite and standard serial i/o modes. for this flash memory, three flash memory modes are available in which to read, program, and erase: the parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and the cpu rewrite mode in which the flash memory can be manipulated by the central processing unit (cpu). summary table 25 lists the summary of the m37641f8 (flash memory ver- sion). this flash memory version has some blocks on the flash memory as shown in figure 88 and each block can be erased. the flash memory is divided into user rom area and boot rom area. in addition to the ordinary user rom area to store the mcu op- eration control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the user s application sys- tem. this boot rom area can be rewritten in only parallel i/o mode. item power source voltage (for program/erase) v pp voltage (for program/erase) flash memory mode erase block division user rom area boot rom area program method erase method program/erase control method number of commands number of program/erase times rom code protection specifications vcc = 3.00 C 3.60 v, 4.50 C 5.25 v (f(x in ) = 24 mhz, = 6 mhz) (note 1) v pp = 4.50 C 5.25 v 3 modes; flash memory can be manipulated as follows: (1) cpu rewrite mode: manipulated by the central processing unit (cpu) (2) parallel i/o mode: manipulated using an external programmer (note 2) (3) standard serial i/o mode: manipulated using an external programmer (note 2) . see figure 79. 1 block (4 kbytes) ( note 3 ) byte program batch erasing/block erasing program/erase control by software command 6 commands 100 times available in parallel i/o mode and standard serial i/o mode notes 1: after programming/erasing at vcc = 3.0 to 3.6 v, the mcu can operate only at vcc = 3.0 to 3.6 v. after programming/erasing at vcc = 4.5 to 5.25 v or programming/erasing with the exclusive external equipment flash programmer, the mcu can operate at both vcc = 3.0 to 3.6 v and 4.15 to 5.25 v. 2: in the parallel i/o mode or the standard serial i/o mode, use the exclusive external equipment flash programmer which supports the 7641 group (flash memory version). 3: the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. this boot rom area can be rewritten in only parallel i/o mode.
7641 group rev.4.00 aug 28, 2006 page 103 of 135 rej03b0191-0400 fig. 88 block diagram of built-in flash memory (1) cpu rewrite mode in cpu rewrite mode, the internal flash memory can be operated on (read, program, or erase) under control of the central process- ing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 88 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite con- trol program must be transferred to internal ram area to be executed before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the stan- dard serial i/o mode becomes unusable.) see figure 88 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p3 6 (ce) pin high, the p8 1 (sclk) pin high, the cnv ss pin high, the cpu starts oper- ating using the control program in the boot rom area. this mode is called the boot mode. block address block addresses refer to the maximum address of each block. these addresses are used in the block erase command. e0 0 0 1 6 user rom area 4 kb y t e s f f f f 1 6 boot rom area n o t e s 1 : t h e b o o t r o m a r e a c a n b e r e w r i t t e n i n o n l y p a r a l l e l i / o m o d e . ( a c c e s s t o a n y o t h e r a r e a s i s i n h i b i t e d . ) 2 : t o s p e c i f y a b l o c k , u s e t h e m a x i m u m a d d r e s s i n t h e b l o c k . p a r a l l e l i / o m o d e c p u r e w r i t e m o d e , s t a n d a r d s e r i a l i / o m o d e b s e l = l bsel = h user area / boot area select bit = 0 user area / boot area select bit = 1 c000 16 block 1 : 8 kbytes b l o c k 2 : 1 6 k b y t e s b l o c k 0 : 8 k b y t e s 8000 16 f0 0 0 1 6 f f f f 1 6 e0 0 0 1 6 user rom area 4 kb y t e s ffff 16 boot rom area c0 0 0 1 6 b l o c k 1 : 8 k b y t e s b l o c k 2 : 1 6 k b y t e s b l o c k 0 : 8 k b y t e s 80 0 0 1 6 f0 0 0 1 6 ffff 16
7641 group rev.4.00 aug 28, 2006 page 104 of 135 rej03b0191-0400 outline performance (cpu rewrite mode) cpu rewrite mode is usable in the single-chip, memory expansion or boot mode. the only user rom area can be rewritten in cpu rewrite mode. in cpu rewrite mode, the cpu erases, programs and reads the in- ternal flash memory by executing software commands. this rewrite control program must be transferred to a memory such as the internal ram before it can be executed. the mcu enters cpu rewrite mode by applying 4.50 v to 5.25 v to the cnv ss pin and setting 1 to the cpu rewrite mode select bit (bit 1 of address 006a 16 ). software commands are accepted once the mode is entered. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 89 shows the flash memory control register. bit 0 is the ry/by status flag used exclusively to read the operat- ing status of the flash memory. during programming and erase operations, it is 0 (busy). otherwise, it is 1 (ready). bit 1 is the cpu rewrite mode select bit. when this bit is set to 1 , the mcu enters cpu rewrite mode. software commands are accepted once the mode is entered. in cpu rewrite mode, the f l a s h m e m o r y c o n t r o l r e g i s t e r ( a d d r e s s 0 0 6 a 1 6 ) f m c r r y / b y s t a t u s f l a g 0 : b u s y ( b e i n g p r o g r a m m e d o r e r a s e d ) 1 : r e a d y c p u r e w r i t e m o d e s e l e c t b i t ( n o t e 2 ) 0 : n o r m a l m o d e ( s o f t w a r e c o m m a n d s i n v a l i d ) 1 : c p u r e w r i t e m o d e ( s o f t w a r e c o m m a n d s a c c e p t a b l e ) c p u r e w r i t e m o d e e n t r y f l a g 0 : n o r m a l m o d e 1 : c p u r e w r i t e m o d e f l a s h m e m o r y r e s e t b i t ( n o t e 3 ) 0 : n o r m a l o p e r a t i o n 1 : r e s e t u s e r r o m a r e a / b o o t r o m a r e a s e l e c t b i t ( n o t e 4 ) 0 : u s e r r o m a r e a a c c e s s e d 1 : b o o t r o m a r e a a c c e s s e d r e s e r v e d b i t s ( i n d e f i n i t e a t r e a d / 0 a t w r i t e ) b0 b7 notes 1 : the contents of flash memory control register are xxx00001 just after reset release. 2 : for this bit to be set to 1 , the user needs to write 0 and then 1 to it in succession. if it is not this procedure, this bit will not be set to 1 . additionally, it is required to ensure that no interrupt will be generated during that interval. use the control program in the area except the built-in flash memory for write to this bit. 3 : this bit is valid when the cpu rewrite mode select bit is 1 . set this bit 3 to 0 subsequently after setting bit 3 to 1 . 4 : use the control program in the area except the built-in flash memory for write to this bit. cpu becomes unable to access the internal flash memory directly. therefore, use the control program in a memory other than inter- nal flash memory for write to bit 1. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing 0 . bit 2 is the cpu rewrite mode entry flag. this flag indicates 1 in cpu rewrite mode, so that reading this flag can check whether cpu rewrite mode has been entered or not. bit 3 is the flash memory reset bit used to reset the control circuit of internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1 , setting 1 for this bit resets the control circuit. to set this bit to 1 , it is necessary to write 0 and then write 1 in succession. to release the reset, it is necessary to set this bit to 0 . bit 4 is the user area/boot area select bit. when this bit is set to 1 , boot rom area is accessed, and cpu rewrite mode in boot rom area is available. in boot mode, this bit is set to 1 auto- matically. reprogramming of this bit must be in a memory other than internal flash memory. figure 90 shows a flowchart for setting/releasing cpu rewrite mode. fig. 89 structure of flash memory control register
7641 group rev.4.00 aug 28, 2006 page 105 of 135 rej03b0191-0400 fig. 90 cpu rewrite mode set/release flowchart e n d start e x e c u t e r e a d a r r a y c o m m a n d o r r e s e t f l a s h m e m o r y b y s e t t i n g f l a s h m e m o r y r e s e t b i t ( b y w r i t i n g 1 a n d t h e n 0 i n s u c c e s s i o n ) ( n o t e 3 ) single-chip mode, memory expansion mode or boot mode s e t c p u m o d e r e g i s t e r s a , b ( n o t e 2 ) using software command execute erase, program, or other operation j u m p t o c o n t r o l p r o g r a m t r a n s f e r r e d i n m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y ( s u b s e q u e n t o p e r a t i o n s a r e e x e c u t e d b y c o n t r o l p r o g r a m i n t h i s m e m o r y ) t r a n s f e r c p u r e w r i t e m o d e c o n t r o l p r o g r a m t o m e m o r y o t h e r t h a n i n t e r n a l f l a s h m e m o r y n o t e s1 : w h e n s t a r t i n g t h e m c u i n t h e s i n g l e - c h i p m o d e o r m e m o r y e x p a n s i o n m o d e , s u p p l y 4 . 5 v t o 5 . 2 5 v t o t h e c n v s s p i n u n t i l c h e c k i n g t h e c p u r e w r i t e m o d e e n t r y f l a g . 2 : s e t t h e m a i n c l o c k a s f o l l o w s d e p e n d i n g o n t h e x i n d i v i d e r s e l e c t b i t o f c l o c k c o n t r o l r e g i s t e r ( b i t 7 o f a d d r e s s 0 0 1 f 1 6 ) : w h e n x i n d i v i d e r s e l e c t b i t = 0 ( = f ( x i n ) / 4 ) , t h e m a i n c l o c k i s 2 4 m h z o r l e s s w h e n x i n d i v i d e r s e l e c t b i t = 1 ( = f ( x i n ) / 2 ) , t h e m a i n c l o c k i s 1 2 m h z o r l e s s . 3 : b e f o r e e x i t i n g t h e c p u r e w r i t e m o d e a f t e r c o m p l e t i n g e r a s e o r p r o g r a m o p e r a t i o n , a l w a y s b e s u r e t o e x e c u t e t h e r e a d a r r a y c o m m a n d o r r e s e t t h e f l a s h m e m o r y . w r i t e 0 t o c p u r e w r i t e m o d e s e l e c t b i t s e t c p u r e w r i t e m o d e s e l e c t b i t t o 1 ( b y w r i t i n g 0 a n d t h e n 1 i n s u c c e s s i o n ) check cpu rewrite mode entry flag s e t t i n g r e l e a s e d
7641 group rev.4.00 aug 28, 2006 page 106 of 135 rej03b0191-0400 notes on cpu rewrite mode the below notes applies when rewriting the flash memory in cpu rewrite mode. during cpu rewrite mode, set the internal clock to 6 mhz or less using the x in divider select bit (bit 7 of address 001f 16 ). the instructions which refer to the internal data of the flash memory cannot be used during cpu rewrite mode . the interrupts cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. reset is always valid. when cnv ss is h at reset release, the program starts from the address stored in addresses fffa 16 and fffb 16 of the boot rom area in order that cpu may start in boot mode.
7641 group rev.4.00 aug 28, 2006 page 107 of 135 rej03b0191-0400 software commands (cpu rewrite mode) table 26 lists the software commands. after setting the cpu rewrite mode select bit of the flash memory control register to 1 , execute a software command to specify an erase or program operation. each software command is explained below. the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the contents of the specified ad- dress are read out at the data bus (db 0 to db 7 ). the read array mode is retained intact until another command is written. the read status register mode is entered by writing the command code 70 16 in the first bus cycle. the contents of the status regis- ter are read out at the data bus (db 0 to db 7 ) by a read in the second bus cycle. the status register is explained in the next section. this command is used to clear the bits sr4 and sr5 of the status register after they have been set. these bits indicate that opera- tion has ended in an error. to use this command, write the command code 50 16 in the first bus cycle. program operation starts when the command code 40 16 is writ- ten in the first bus cycle. then, if the address and data to program are written in the 2nd bus cycle, program operation (data program- ming and verification) will start. whether the write operation is completed can be confirmed by _____ reading the status register or the ry/by status flag of the flash memory control register. when the program starts, the read status table 26 list of software commands (cpu rewrite mode) register mode is entered automatically and the contents of the sta- tus register is read at the data bus (db 0 to db 7 ). the status register bit 7 (sr7) is set to 0 at the same time the write opera- tion starts and is returned to 1 upon completion of the write operation. in this case, the read status register mode remains ac- tive until the next command is written. ____ the ry/by status flag is 0 (busy) during write operation and 1 (ready) when the write operation is completed as is the status reg- ister bit 7. at program end, program results can be checked by reading bit 4 (sr4) of the status register. fig. 91 program flowchart command p r o g r a m c l e a r s t a t u s r e g i s t e r r e a d a r r a y r e a d s t a t u s r e g i s t e r x x f i r s t b u s c y c l e second bus cycle f f 1 6 7 0 1 6 5 0 1 6 4 0 1 6 write write write write xs r d read w r i t e e r a s e a l l b l o c k s2 0 1 6 write x 20 16 w r i t e (note 1) wa (note 2) wd (note 2) block erase 2 0 1 6 write d0 16 w r i t eb a (note 3) mode address mode a d d r e s s data ( d b 0 t o d b 7 ) ( d b 0 t o d b 7 ) (note 4) n o t e s 1 : srd = status register data 2: wa = write address, wd = write data 3: ba = block address to be erased (input the maximum address of each block.) 4: x denotes a given address in the user rom area . c y c l e n u m b e r 1 2 1 2 2 2 x x x x data s t a r t write 40 16 s t a t u s r e g i s t e r r e a d program completed n o y e s w r i t e a d d r e s s w r i t e d a t a sr4 = 0 ? program error n o y e s sr7 = 1 ? or ry/by = 1 ? w r i t e
7641 group rev.4.00 aug 28, 2006 page 108 of 135 rej03b0191-0400 by writing the command code 20 16 in the first bus cycle and the confirmation command code 20 16 in the second bus cycle that follows, the operation of erase all blocks (erase and erase verify) starts. whether the erase all blocks command is terminated can be con- ____ firmed by reading the status register or the ry/by status flag of flash memory control register. when the erase all blocks operation starts, the read status register mode is entered automatically and the contents of the status register can be read out at the data bus (db 0 to db 7 ). the status register bit 7 (sr7) is set to 0 at the same time the erase operation starts and is returned to 1 upon completion of the erase operation. in this case, the read status register mode remains active until another command is written. ____ the ry/by status flag is 0 during erase operation and 1 when the erase operation is completed as is the status register bit 7 (sr7). after the erase all blocks end, erase results can be checked by reading bit 5 (srs) of the status register. for details, refer to the section where the status register is detailed. by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 and the blobk address in the second bus cycle that follows, the block erase (erase and erase verify) operation starts for the block address of the flash memory to be specified. whether the block erase operation is completed can be confirmed ____ by reading the status register or the ry/by status flag of flash memory control register. at the same time the block erase opera- tion starts, the read status register mode is automatically entered, so that the contents of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the block erase operation starts and is returned to 1 upon completion of the block erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) is writ- ten. ____ the ry/by status flag is 0 during block erase operation and 1 when the block erase operation is completed as is the status reg- ister bit 7. after the block erase ends, erase results can be checked by read- ing bit 5 (srs) of the status register. for details, refer to the section where the status register is detailed. w r i t e 2 0 1 6 20 16 /d0 16 block address erase completed no y e s s t a r t w r i t e s r 5 = 0 ? e r a s e e r r o r y e s no 2 0 1 6 : e r a s e a l l b l o c k s c o m m a n d d 0 1 6 : b l o c k e r a s e c o m m a n d s r 7 = 1 ? o r r y / b y = 1 ? status register read fig. 92 erase flowchart
7641 group rev.4.00 aug 28, 2006 page 109 of 135 rej03b0191-0400 symbol table 27 definition of each bit in status register (srd) status register (srd) the status register shows the operating status of the flash memory and whether erase operations and programs ended suc- cessfully or in error. it can be read in the following ways: (1) by reading an arbitrary address from the user rom area after writing the read status register command (70 16 ) (2) by reading an arbitrary address from the user rom area in the period from when the program starts or erase operation starts to when the read array command (ff 16 ) is input. also, the status register can be cleared by writing the clear status register command (50 16 ). after reset, the status register is set to 80 16 . table 27 shows the status register. each bit in this register is ex- plained below. ? sequencer status (sr7) the sequencer status indicates the operating status of the flash memory. this bit is set to 0 (busy) during write or erase operation and is set to 1 when these operations ends. after power-on, the sequencer status is set to 1 (ready). ? erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . ? program status (sr4) the program status indicates the operating status of write opera- tion. when a write error occurs, it is set to 1 . the program status is set to 0 when it is cleared. if 1 is written for any of the sr5 and sr4 bits, the program, erase all blocks, and block erase commands are not accepted. before executing these commands, execute the clear status regis- ter command (50 16 ) and clear the status register. also, if any commands are not correct, both sr5 and sr4 are set to 1 . sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 status name sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
7641 group rev.4.00 aug 28, 2006 page 110 of 135 rej03b0191-0400 full status check by performing full status check, it is possible to know the execu- tion results of erase and program operations. figure 93 shows a fig. 93 full status check flowchart and remedial procedure for errors full status check flowchart and the action to be taken when each error occurs. r e a d s t a t u s r e g i s t e r sr4 = 1 and sr5 = 1 ? n o y e s s r 5 = 0 ? y e s erase error n o s r 4 = 0 ? yes n o c o m m a n d s e q u e n c e e r r o r p r o g r a m e r r o r e n d ( e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. note : when one of sr5 and sr4 is set to 1 , none of the read aray, the program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. should a program error occur, the block in error cannot be used.
7641 group rev.4.00 aug 28, 2006 page 111 of 135 rej03b0191-0400 functions to inhibit rewriting flash memory version to prevent the contents of internal flash memory from being read out or rewritten easily, this mcu incorporates a rom code protect function for use in parallel i/o mode and an id code check func- tion for use in standard serial i/o mode. the rom code protect function is the function to inhibit reading out or modifying the contents of internal flash memory by using the rom code protect control (address ffc9 16 ) in parallel i/o mode. figure 94 shows the rom code protect control (address ffc9 16 ). (this address exists in the user rom area.) if one or both of the pair of rom code protect bits is set to 0 , the rom code protect is turned on, so that the contents of internal flash memory are protected against readout and modification. the rom code protect is implemented in two levels. if level 2 is se- lected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00 , the rom code protect is turned off, so that the contents of internal flash memory can be read out or modified. once the rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/o or cpu rewrite mode to rewrite the contents of the rom code pro- tect reset bits. fig. 94 structure of rom code protect control r o m c o d e p r o t e c t c o n t r o l ( a d d r e s s f f c 9 1 6 ) ( n o t e 1 ) r o m c p r e s e r v e d b i t s ( 1 a t r e a d / w r i t e ) r o m c o d e p r o t e c t l e v e l 2 s e t b i t s ( r o m c p 2 ) ( n o t e s 2 , 3 ) b 3 b 2 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d r o m c o d e p r o t e c t r e s e t b i t s ( n o t e 4 ) b 5 b 4 0 0 : p r o t e c t r e m o v e d 0 1 : p r o t e c t s e t b i t s e f f e c t i v e 1 0 : p r o t e c t s e t b i t s e f f e c t i v e 1 1 : p r o t e c t s e t b i t s e f f e c t i v e r o m c o d e p r o t e c t l e v e l 1 s e t b i t s ( r o m c p 1 ) ( n o t e 2 ) b 7 b 6 0 0 : p r o t e c t e n a b l e d 0 1 : p r o t e c t e n a b l e d 1 0 : p r o t e c t e n a b l e d 1 1 : p r o t e c t d i s a b l e d b0 b 7 n o t e s1 : t h i s a r e a i s o n t h e r o m i n t h e m a s k r o m v e r s i o n . 2 : w h e n r o m c o d e p r o t e c t i s t u r n e d o n , t h e i n t e r n a l f l a s h m e m o r y i s p r o t e c t e d a g a i n s t r e a d o u t o r m o d i f i c a t i o n i n p a r a l l e l i / o m o d e . 3 : w h e n r o m c o d e p r o t e c t l e v e l 2 i s t u r n e d o n , r o m c o d e r e a d o u t b y a s h i p m e n t i n s p e c t i o n l s i t e s t e r , e t c . a l s o i s i n h i b i t e d . 4 : t h e r o m c o d e p r o t e c t r e s e t b i t s c a n b e u s e d t o t u r n o f f r o m c o d e p r o t e c t l e v e l 1 a n d r o m c o d e p r o t e c t l e v e l 2 . h o w e v e r , s i n c e t h e s e b i t s c a n n o t b e m o d i f i e d i n p a r a l l e l i / o m o d e , t h e y n e e d t o b e r e w r i t t e n i n s t a n d a r d s e r i a l i / o m o d e o r c p u r e w r i t e m o d e . 1 1
7641 group rev.4.00 aug 28, 2006 page 112 of 135 rej03b0191-0400 id code check function (in standard serial i/o mode) use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the pro- grammer is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the programmer are not accepted. the id code consists of 8-bit data, and its areas are ffc2 16 to ffc8 16 . write a program which has had the id code preset at these addresses to the flash memory. fig. 95 id code store addresses rom code protect control id7 id6 id5 id4 id3 id2 id1 ffc9 16 ffc8 16 ffc7 16 ffc6 16 ffc5 16 ffc4 16 ffc3 16 ffc2 16 address interrupt vector area
7641 group rev.4.00 aug 28, 2006 page 113 of 135 rej03b0191-0400 (2) parallel i/o mode parallel i/o mode is the mode which parallel output and input soft- ware command, address, and data required for the operations (read, program, erase, etc.) to a built-in flash memory. use the ex- clusive external equipment flash programmer which supports the 7641 group (flash memory version). refer to each programmer maker s handling manual for the details of the usage. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in fig- ure 88 can be rewritten. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its block is shown in figure 88. the boot rom area is 4 kbytes in size. it is located at addresses f000 16 through ffff 16 . make sure program and block erase opera- tions are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 4 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial i/o mode, you do not need to write to the boot rom area.
7641 group rev.4.00 aug 28, 2006 page 114 of 135 rej03b0191-0400 (3) standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, pro- gram, erase, etc.) the internal flash memory. this i/o is clock synchronized serial. this mode requires the exclusive external equipment (flash programmer). the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu rewrite mode), rewrite data input and so forth. the standard serial i/o mode is started by connecting h to the p3 6 (ce) pin and h to the p8 1 (sclk) pin and h to the cnv ss pin (apply 4.5 v to 5.25 v to vpp from an external source), and releasing the re- set operation. (in the ordinary microcomputer mode, set cnvss pin to l level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accordingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in parallel i/o mode. figures 96 and 97 show the pin connections for the standard serial i/o mode. in standard serial i/o mode, serial data i/o uses the four serial i/o pins sclk, srxd, stxd and srdy (busy). the sclk pin is the transfer clock input pin through which an external transfer clock is input. the stxd pin is for cmos output. the srdy (busy) pin outputs l level when ready for reception and h level when re- ception starts. serial data i/o is transferred serially in 8-bit units. in standard serial i/o mode, only the user rom area shown in figure 88 can be rewritten. the boot rom area cannot. in standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, commands sent from the peripheral unit (programmer) are not accepted unless the id code matches. outline performance (standard serial i/o mode) in standard serial i/o mode, software commands, addresses and data are input and output between the mcu and peripheral units (flash programer, etc.) using 4-wire clock-synchronized serial i/o. in reception, software commands, addresses and program data are synchronized with the rise of the transfer clock that is input to the sclk pin, and are then input to the mcu via the srxd pin. in transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the stxd pin. the stxd pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the srdy (busy) pin is h level. accordingly, always start the next transfer after the srdy (busy) pin is l level. also, data and status registers in a memory can be read after in- putting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following explains software commands, status registers, etc.
7641 group rev.4.00 aug 28, 2006 page 115 of 135 rej03b0191-0400 table 28 description of pin function (standard serial i/o mode) p i n n a m es i g n a l n a m ei / of u n c t i o n v cc ,v ss p o w e r s u p p l y i n p u ta p p l y 4 . 5 0 v C 5 . 2 5 v f o r 5 v v e r s i o n o r 3 . 0 0 v C 3 . 6 0 v f o r 3 v v e r s i o n t o t h e v c c p i n . a p p l y 0 v t o t h e v s s p i n . c n v s s c n v s s t h i s c o n t r o l s t h e m c u o p e r a t i n g m o d e . c o n n e c t t h i s p i n t o v p p ( = 4 . 5 0 v C 5 . 2 5 v i r e s e t i n p u tt o r e s e t , i n p u t l l e v e l f o r 2 0 c y c l e s o r l o n g e r c l o c k s o f . i r e s e t x i n c l o c k i n p u t c o n n e c t a c e r a m i c o r c r y s t a l r e s o n a t o r b e t w e e n t h e x i n a n d x o u t p i n s . w h e n i n p u t t i n g a n e x t e r n a l l y d e r i v e d c l o c k , i n p u t i t f r o m x i n a n d l e a v e x o u t o p e n . x o u t c l o c k o u t p u t a v c c , a v s s a n a l o g p o w e r s u p p l y i n p u t l p fl p fo l o o p f i l t e r f o r t h e f r e q u e n c y s y n t h e s i z e r . w h e n t h i s p i n i s n o t u s e d , l e a v e t h i s o p e n . e x t . c a p 3 . 3 v l i n e p o w e r s u p p l y i n p u t i p0 0 to p0 7 i / o u s b d + u s b d + s i g n a l p o r t . w h e n t h i s p i n i s n o t u s e d , i n p u t h l e v e l . u s b d + usb d- u s b d - p 1 0 t o p 1 7 p8 0 busy output p8 1 sclk input i / o i/o o i i a p p l y 4 . 5 0 v C 5 . 2 5 v f o r 5 v v e r s i o n o r 3 . 0 0 v C 3 . 6 0 v f o r 3 v v e r s i o n t o t h e a v c c p i n . a p p l y 0 v t o t h e a v s s p i n . usb d- signal port. when this pin is not used, input l level. p o w e r s u p p l y i n p u t p i n f o r 3 . 3 v u s b l i n e d r i v e r . w h e n t h i s p i n i s n o t u s e d , i n p u t h l e v e l . when these ports are not used, input l or h level, or leave them open in output mode. i/o port p0 i/o i / o p o r t p 1 i/o p2 0 to p2 7 i/o port p2 p 3 0 t o p 3 5 , p 3 7 i / o p 4 0 t o p 4 4 i / o p o r t p 3i / o i / o p o r t p 4 i / o p 5 0 t o p 5 7 i / o p o r t p 5 i/o p6 0 to p6 7 i/o port p6 i/o p7 0 to p7 4 i/o port p7 t h i s i s a b u s y o u t p u t p i n . this is a serial clock input pin. p 8 2 s r x d in p u tt h i s i s a s e r i a l d a t a i n p u t p i n . o p8 3 stxdoutput this is a serial data output pin. p8 4 to p8 7 w h e n t h e s e p o r t s a r e n o t u s e d , i n p u t l o r h l e v e l , o r l e a v e t h e m o p e n i n o u t p u t m o d e . i/o port p8 i/o p 3 6 c e i n p u t i when these ports are not used, input l or h level, or leave them open in output mode. in p u t h l e v e l .
7641 group rev.4.00 aug 28, 2006 page 116 of 135 rej03b0191-0400 fig. 96 pin connection diagram in standard serial i/o mode (1) p7 4 /obf 1 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 2 5 26 27 2 8 2 9 3 0 31 3 2 3 3 3 4 3 5 36 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p 6 1 / d q 1 p 5 6 / r ( e ) p 5 5 / a 0 p 5 3 / i b f 0 p 5 2 / o b f 0 c n v s s r e s e t a v c c a v s s p 4 4 / c n t r 1 p 8 7 / r t s 1 p8 6 /cts 1 v c c p 5 0 / x c i n v s s x i n x o u t p 5 1 / t o u t / x c o u t l p f p8 5 /urxd 1 p 8 4 / u t x d 1 p 3 2 p 3 1 m 3 7 6 4 1 f 8 f p p 6 0 / d q 0 p 5 7 / w / ( r / w ) p 5 4 / s 0 2 1 2 2 2 3 2 4 p 4 3 / c n t r 0 p 4 2 / i n t 1 p 4 1 / i n t 0 p 4 0 / e d m a 6 1 6 2 6 3 6 4 p8 3 /rts 2 /stxd p8 2 /cts 2 /srxd p8 1 /urxd 2 /sclk p8 0 /utxd 2 /srdy p 3 7 / r d p3 6 /wr p3 5 /sync out p 3 4 / out p 3 3 / d m a o u t p3 0 /rdy p 1 7 / a b 1 5 { a b 1 5 } p 1 6 / a b 1 4 { a b 1 4 } p 1 5 / a b 1 3 { a b 1 3 } p 1 4 / a b 1 2 { a b 1 2 } p 1 3 / a b 1 1 { a b 1 1 } p 1 2 / a b 1 0 { a b 1 0 } p 1 1 / a b 9 { a b 9 } p 1 0 / a b 8 { a b 8 } p 0 7 / a b 7 { a b 7 } p 0 6 / a b 6 { a b 6 } p 0 5 / a b 5 { a b 5 } p 0 4 / a b 4 { a b 4 } p 0 3 / a b 3 { a b 3 } p 0 2 / a b 2 { a b 2 } p 0 1 / a b 1 { a b 1 } p 0 0 / a b 0 { a b 0 } p 2 7 / d b 7 { d b 7 } p 2 6 / d b 6 { d b 6 } p 2 5 / d b 5 { d b 5 } p 2 4 / d b 4 { d b 4 } p 2 3 / d b 3 { d b 3 } p 2 2 / d b 2 { d b 2 } p 2 1 / d b 1 { d b 1 } p 2 0 / d b 0 { d b 0 } p 7 3 / i b f 1 / h l d a p 7 2 / s 1 p7 1 /hold p 7 0 / s o f u s b d + u s b d - e x t . c a p v s s v c c p6 7 /dq 7 p 6 6 / d q 6 p 6 5 / d q 5 p6 4 /dq 4 p 6 3 / d q 3 p6 2 /dq 2 busy s c l k cnv ss sclk reset ce 4 . 5 t o 5 . 2 5 v v c c ( note ) v ss v cc v cc v cc v ss mode setup method signal value connect to oscillator circuit. package outline: prqp0080gb-a srxd stxd r e s e t v p p note : it is necessary to apply vcc only when reset is released. c e
7641 group rev.4.00 aug 28, 2006 page 117 of 135 rej03b0191-0400 fig. 97 pin connection diagram in standard serial i/o mode (2) p7 4 /obf 1 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 25 26 27 28 29 30 31 32 33 34 35 36 37 3 8 3 9 40 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 65 66 6 7 6 8 6 9 7 0 7 1 7 2 7 3 74 7 5 76 7 7 7 8 79 8 0 p 6 1 / d q 1 p 5 6 / r ( e ) p 5 5 / a 0 p 5 3 / i b f 0 p 5 2 / o b f 0 c n v s s r e s e t a v c c a v s s p 4 4 / c n t r 1 p8 7 /rts 1 p8 6 /cts 1 v c c p 5 0 / x c i n v s s x i n x o u t p 5 1 / t o u t / x c o u t l p f p8 5 /urxd 1 p8 4 /utxd 1 p3 2 p3 1 m37641f8hp p 6 0 / d q 0 p 5 4 / s 0 21 22 23 24 p 4 3 / c n t r 0 p 4 2 / i n t 1 p4 1 /int 0 6 1 6 2 6 3 6 4 p8 3 /rts 2 /stxd p8 2 /cts 2 /srxd p8 1 /urxd 2 /sclk p8 0 /utxd 2 /srdy p3 7 /rd p3 6 /wr p3 5 /sync out p3 4 / out p3 3 /dma out p3 0 /rdy p1 7 /ab 15 {ad 15 } p1 6 /ab 14 {ad 14 } p 2 1 / d b 1 p 2 0 / d b 0 u s b d + u s b d - ext.cap v s s v cc p 6 7 / d q 7 p 6 6 / d q 6 p6 5 /dq 5 p 6 4 / d q 4 p6 3 /dq 3 p 6 2 / d q 2 p4 0 /edma p 7 1 / h o l d p 7 0 / s o f p 5 7 / w / ( r / w ) p7 2 /s 1 p7 3 /ibf 1 /hlda v cc v ss p 1 5 / a b 1 3 { a b 1 3 } p 1 4 / a b 1 2 { a b 1 2 } p 1 3 / a b 1 1 { a b 1 1 } p 1 2 / a b 1 0 { a b 1 0 } p 1 1 / a b 9 { a b 9 } p 1 0 / a b 8 { a b 8 } p 0 7 / a b 7 { a b 7 } p 0 6 / a b 6 { a b 6 } p 0 5 / a b 5 { a b 5 } p 0 4 / a b 4 { a b 4 } p 0 3 / a b 3 { a b 3 } p 0 2 / a b 2 { a b 2 } p 0 1 / a b 1 { a b 1 } p 0 0 / a b 0 { a b 0 } p 2 7 / d b 7 { d b 7 } p 2 6 / d b 6 { d b 6 } p 2 5 / d b 5 { d b 5 } p 2 4 / d b 4 { d b 4 } p 2 3 / d b 3 { d b 3 } p 2 2 / d b 2 { d b 2 } c n v s s s c l k r e s e t c e m o d e s e t u p m e t h o d signal v a l u e connect to oscillator circuit. package outline: plqp0080kb-a busy s c l k s r x d s t x d r e s e t v p p 4.5 to 5.25 v v cc ( note ) v ss v cc v cc n o t e : i t i s n e c e s s a r y t o a p p l y v c c o n l y w h e n r e s e t i s r e l e a s e d . c e
7641 group rev.4.00 aug 28, 2006 page 118 of 135 rej03b0191-0400 software commands (standard serial i/o mode) table 29 lists software commands. in standard serial i/o mode, erase, program and read are controlled by transferring software 2nd byte address (middle) 3rd byte address (high) 4th byte data output 5th byte data output 6th byte data output ..... data output to 259th byte data input to 259th byte ff 16 when id is not verified not acceptable 1st byte transfer notes1: shading indicates transfer from the internal flash memory microcomputer to a programmer. all other data is transferred from an external equipment (programmer) to the internal flash memory microcomputer. 2: srd refers to status register data. srd1 refers to status register 1 data. 3: all commands can be accepted for the products of which boot rom area is totally blank. 4: address low is ab 0 to ab 7 ; address middle is ab 8 to ab 15 ; address high is ab 16 to ab 23 . commands via the srxd pin. software commands are explained here below. table 29 software commands (standard serial i/o mode) 1 page read 41 16 address (middle) address (high) data input data input data input not acceptable not acceptable not acceptable 20 16 address (middle) address (high) d0 16 a7 16 d0 16 70 16 srd output srd1 output acceptable 50 16 not acceptable f5 16 address (low) size (low) address (middle) size (high) address (high) check- sum id size id1 to id7 acceptable fa 16 data input to required number of times not acceptable fb 16 version data output address (middle) version data output address (high) version data output data output version data output data output version data output data output version data output to 9th byte data output to 259th byte acceptable not acceptable fc 16 control command 2 page program 3 block erase 4 erase all blocks 5 read status register 6 clear status register 7 id code check 8 download function 9 version data output function 10 boot rom area output function
7641 group rev.4.00 aug 28, 2006 page 119 of 135 rej03b0191-0400 this command reads status information. when the 70 16 com- mand code is transferred with the 1st byte, the contents of the status register (srd) with the 2nd byte and the contents of status register 1 (srd1) with the 3rd byte are read. this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses ab 8 to ab 15 and ab 16 to ab 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (db 0 to db 7 ) for the page (256 bytes) specified with addresses ab 8 to ab 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. data0 data255 ab 8 to ab 15 ab 16 to ab 23 f f 1 6 s c l k s r x d s t x d s r d y ( b u s y ) s r d o u t p u t s r d 1 o u t p u t s c l k s r x d s t x d s r d y ( b u s y ) 70 16 fig. 98 timing for page read fig. 99 timing for reading status register
7641 group rev.4.00 aug 28, 2006 page 120 of 135 rej03b0191-0400 fig. 100 timing for clear status register this command clears the bits (sr3 to sr5) which are set when the status register operation ends in error. when the 50 16 com- mand code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the srdy (busy) signal changes from h to l level. sclk srxd stxd srdy (busy) 50 16 a b 8 t o a b 1 5 a b 1 6 t o a b 2 3 4 1 1 6 d a t a 0 d a t a 2 5 5 s c l k s r x d s t x d s r d y ( b u s y ) this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page pro- gram command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses ab 8 to ab 15 and ab 16 to ab 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (db 0 to db 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is auto- matically written. when reception setup for the next 256 bytes ends, the srdy (busy) signal changes from h to l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. fig. 101 timing for page program
7641 group rev.4.00 aug 28, 2006 page 121 of 135 rej03b0191-0400 this command erases the contents of the specifided block. ex- ecute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses ab 8 to ab 15 and ab 16 to ab 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specifided block in the flash memory. set the addresses ab 8 to ab 23 to the maximum address of the specified block. 20 16 d 0 1 6 s c l k s r x d s t x d s r d y ( b u s y ) a b 8 t o a b 1 5 a b 1 6 t o a b 2 3 when block erasing ends, the srdy (busy) signal changes from h to l level. the result of the erase operation can be known by reading the status register. for more information, see the section on the status register. fig. 102 timing for block erasing this command erases the contents of all blocks. execute the erase all blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when erase all blocks end, the srdy (busy) signal changes from h to l level. the result of the erase operation can be known by reading the status register. a7 16 d 0 1 6 s c l k s r x d s t x d s r d y ( b u s y ) fig. 103 timing for erase all blocks
7641 group rev.4.00 aug 28, 2006 page 122 of 135 rej03b0191-0400 this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fig. 104 timing for download fa 16 program data p r o g r a m d a t a data size (low) c h e c k s u m s c l k s r x d s t x d s r d y ( b u s y ) d a t a s i z e ( h i g h )
7641 group rev.4.00 aug 28, 2006 page 123 of 135 rej03b0191-0400 this command outputs the version information of the control pro- gram stored in the boot rom area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte on- ward. this data is composed of 8 ascii code characters. fig. 105 timing for version information output fb 16 x v e r sclk srxd stxd srdy (busy) this command reads the control program stored in the boot rom area in page (256 bytes) unit. execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses ab 8 to ab 15 and ab 16 to ab 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (db 0 to db 7 ) for the page (256 bytes) specified with addresses ab 8 to ab 23 will be output se- quentially from the smallest address first synchronized with the fall of the clock. fig. 106 timing for boot rom area output f c 1 6 a b 8 t o a b 1 5 a b 1 6 t o a b 2 3 d a t a 0d a t a 2 5 5 scl k srx d stx d srdy(busy)
7641 group rev.4.00 aug 28, 2006 page 124 of 135 rej03b0191-0400 this command checks the id code. execute the boot id check command as explained here following. when the flash memory is not blank, the id code sent from the se- rial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the serial programmer is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses ffc2 16 to ffc8 16 . write a program into the flash memory, which already has the id code set for these addresses. fig. 107 timing for id check id size i d 1 i d 7 f 5 1 6 c2 16 f f 1 6 0 0 1 6 s c l k s r x d s t x d s r d y ( b u s y ) rom code protect control id7 id6 id5 id4 id3 id2 id1 ffc9 16 ffc8 16 ffc7 16 ffc6 16 ffc5 16 ffc4 16 ffc3 16 ffc2 16 address interrupt vector area fig. 108 id code storage addresses (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses ab 0 to ab 7 , ab 8 to ab 15 and ab 16 to ab 23 ( 00 16 ) of the 1st byte of the id code with the 2nd and 3rd re- spectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) transfer the id code with the 6th byte onward, starting with the 1st byte of the code.
7641 group rev.4.00 aug 28, 2006 page 125 of 135 rej03b0191-0400 the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 30 lists the definition of each status register bit. after releas- ing the reset, the status register becomes 80 16 . ? sequencer status (sr7) the sequencer status indicates the operating status of the the flash memory. after power-on and recover from deep power down mode, the se- quencer status is set to 1 (ready). this status bit is set to 0 (busy) during write or erase operation and is set to 1 upon completion of these operations. ? erase status (sr5) the erase status indicates the operating status of erase operation. if an erase error occurs, it is set to 1 . when the erase status is cleared, it is set to 0 . ? program status (sr4) the program status indicates the operating status of write opera- tion. if a program error occurs, it is set to 1 . when the program status is cleared, it is set to 0 . srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) definition 1 0 table 30 definition of each bit of status register (srd) status name sequencer status reserved erase status program status reserved reserved reserved reserved ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
7641 group rev.4.00 aug 28, 2006 page 126 of 135 rej03b0191-0400 the status register 1 indicates the status of serial communica- tions, results from id checks and results from check sum comparisons. it can be read after the status register (srd) by writ- ing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 31 lists the definition of each status register 1 bit. this regis- ter becomes 00 16 when power is turned on and the flag status is maintained even after the reset. table 31 definition of each bit of status register 1 (srd1) 00 not verified 01 verification mismatch 10 reserved 11 verified sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) boot update completed bit reserved reserved checksum match bit id code check completed bits data reception time out reserved 1 update completed - - match time out - 0 not update - - mismatch normal operation - definition srd1 bits status name ? boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the download function. ? check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execution using the download func- tion. ? id code check completed bits (sr11 and sr10) these flags indicate the result of id code checks. some com- mands cannot be accepted without an id code check. ? data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the re- ceived data is discarded and the mcu returns to the command wait state.
7641 group rev.4.00 aug 28, 2006 page 127 of 135 rej03b0191-0400 full status check results from executed erase and program operations can be known by running a full status check. figure 109 shows a flow- chart of the full status check and explains how to remedy errors which occur. r e a d s t a t u s r e g i s t e r s r 4 = 1 a n d s r5 = 1 ? n o y e s s r 5 = 0 ? y e s er a s e e r r o r n o s r 4 = 0 ? y e s no c o m m a n d s e q u e n c e e r r o r program error e n d ( e r a s e , p r o g r a m ) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should an erase error occur, the block in error cannot be used. note : when one of sr5 to sr4 is set to 1 , none of the page read, program, erase all blocks, and block erase commands is accepted. execute the clear status register command (50 16 ) before executing these commands. s h o u l d a p r o g r a m e r r o r o c c u r , t h e b l o c k i n e r r o r c a n n o t b e u s e d . fig. 109 full status check flowchart and remedial procedure for errors
7641 group rev.4.00 aug 28, 2006 page 128 of 135 rej03b0191-0400 example circuit application for standard serial i/o mode figure 110 shows a circuit application for the standard serial i/o mode. control pins will vary according to a programmer, therefore see a programmer manual for more information. srdy (busy) s c l k s r x d s t x d c n v s s c l o c k i n p u t b u s y o u t p u t data input d a t a o u t p u t m37641f8 notes 1: control pins and external circuitry will vary according to a programmer. for more information, see the programmer manual. 2: in this example, the vpp power supply is supplied from an external source (programmer). to use the user s power source, connect to 4.5 v to 5.25 v. v pp power source input p 3 6 / w r ( c e ) fig. 110 example circuit application for standard serial i/o mode
7641 group rev.4.00 aug 28, 2006 page 129 of 135 rej03b0191-0400 notes on programming processor status register ?the contents of the processor status register (ps) after a reset are undefined, except for the interrupt disable flag (i) which is 1. after a reset, initialize flags which affect program execution. in particular, it is essential to initialize the index x mode (t) and the decimal mode (d) flags because of their effect on calculations. ?to reference the contents of the processor status register (ps), execute the php instruction once then read the contents of (s+1). if necessary, execute the plp instruction to return the ps to its original status. a nop instruction must be executed after every plp instruction. ?a sei instruction must be executed before every plp instruction. a nop instruction must be executed before every cli instruction. brk instruction it can be detected that the brk instruction interrupt event or the least priority interrupt event by referring the stored b flag state. refer to the stored b flag state in the interrupt routine. decimal calculations when decimal mode is selected, the values of the v flags are in- valid. the carry flag (c) is set to 1 if a carry is generated as a result of the calculation, or is cleared to 0 if a borrow is generated. to de- termine whether a calculation has generated a carry, the c flag must be initialized to 0 before each calculation. to check for a borrow, the c flag must be initialized to 1 before each calcula- tion. multiplication and division instructions ?the index x mode (t) and the decimal mode (d) flags do not af- fect the mul and div instruction. instruction execution time the instruction execution time is obtained by multiplying the fre- quency of the internal clock by the number of cycles needed to execute an instruction. the number of cycles required to execute an instruction is shown in the list of machine instructions. timers ?if a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1). ?p5 1 /x cout /t out pin cannot function as an i/o port when x cin - x cout is oscillating. when x cin - x cout oscillation is not used or x cout oscillation drive is disabled, this pin can function as the t out output pin of the timer 1 or 2. when using the t out output function and f(x cin ) divided by 2 is used as the timer 1 count source (bit 2 of t123m = 1), disable x cout oscillation drive (bit 5 of ccr = 1). ports ?when the data register (port latch) of an i/o port is modified with the bit managing instruction ( seb , clb instructions) the value of the unspecified bit may be changed. ?in standby state (the stop mode by executing the stp instruction, and the wait mode by executing the wit instruction) for low- power dissipation, do not make input levels of an i/o port undefined, especially for i/o ports of the p-channel and the n- channel open-drain. pull-up (connect the port to vcc) or pull-down (connect the port to vss) these ports through a resistor. when determining a resistance value, note the following points: (1) external circuit (2) variation of output levels during the ordinary operation when using built-in pull-up or pull-down resistor, note on varied current values. (1) when setting as an input port : fix its input level (2) when setting as an output port : prevent current from flowing out to external serial i/o do not write to the serial i/o shift register during a transfer when in spi compatible mode. uart ?the all error flags per, fer, oer and ser are cleared to 0 when the uartx status register is read, at the hardware reset or initialization by setting the transmit initialization bit. these flags are also cleared to 0 by execution of bit test instructions such as bbc and bcs . ?the transmission interrupt request bit is set and the interrupt re- quest is generated by setting the transmit enable bit to 1 even when selecting timing that either of the following flags is set to 1 as timing where the transmission interrupt is generated: (1) transmit buffer empty flag is set to 1 (2) transmit complete flag is set to 1. therefore, when the transmit interrupt is used, set the transmit in- terrupt enable bit to transmit enabled as the following sequence: (1) transmit enable bit is set to 1 (2) transmit interrupt request bit is set to 0 (3) transmit interrupt enable bit is set to 1. ?do not update a value of uartx baud rate generator in the con- dition of transmission enabled or reception enabled. disable transmission and reception before updating the value. if the former data remains in the uartx transmit buffer registers 1 and 2 when transmission is enabled, an undefined data might be out- put. ?the receive buffer full interrupt request is not generated if receive errors are detected at receiving.
7641 group rev.4.00 aug 28, 2006 page 130 of 135 rej03b0191-0400 usb ?when the usb reset interrupt status flag is kept at 1, all other flags in the usb internal registers (addresses 0050 16 to 005f 16 ) will return to their reset status. however, the following registers are not affected by the usb reset: usb control register (address 0013 16 ), frequency synthesizer control register (address 006c 16 ), clock control register (address 001f 16 ), and usb end- point-x fifo register (addresses 0060 16 to 0064 16 ). ?when not using the usb function, set the usb line driver supply enable bit of the usb control register (address 0013 16 ) to 1 for power supply to the internal circuits (at vcc = 5v). ?when using an isochronous transfer, set the flush bit (bit 6 of address 0059 16 and bit 6 of address 005a 16 ) as follows: in fifo: use auto_flush bit (bit 6 of address 0058 16 ) out fifo: when out_pkt_rdy bit is 1, set flush bit to 1 ?when the usb sof port select bit is 1, the reference pulse of 83.3 ns ( = 12 mhz) is output from the p7 0 /sof pin and syn- chronized with the sof packet. ?if a character bit length is 7 bits, bit 7 of the uartx transmit/re- ceive buffer register 1 and bits 0 to 7 of the uartx transmit/ receive buffer register 2 are ignored at transmitting; they are in- valid at receiving. if a character bit length is 8 bits, bits 0 to 7 of the uartx transmit/ receive buffer register 2 are ignored at transmitting; they are in- valid at receiving. if a character bit length is 9 bits, bits 1 to 7 of the uartx transmit/ receive buffer register 2 are ignored at transmitting; they are 0 at receiving. ?the in_pkt_rdy bit can be set by software even when using the auto_set function. ?when writing to usb-related registers, set the usb clock enable bit to 1, then perform the write after four cycle waits. ?when using the mcu at vcc = 3.3v, set the usb line driver sup- ply enable bit to 0 (line driver disable). note that setting the usb line driver current control bit (usbc3) doesnt affect the usb operation. ?read one packet data from the out fifo before clearing the out_pkt_rdy flag. if the out_pkt_rdy flag is cleared while one packet data is being read, the internal read pointer can- not operate normally. ?use the auto_flush bit (bit 6 of address 0058 16 ) in double buffer mode. ?use the transfer instructions such as lda and sta to set the reg- isters: usb interrupt status registers 1, 2 (addresses 0052 16 , 0053 16 ); usb endpoint 0 in control register (address 0059 16 ); usb endpoint x in control register (address 0059 16 ); usb end- point x out control register (address 005a 16 ). do not use the read-modify-write instructions such as the seb or the clb in- struction. when writing to bits shown by table 32 using the transfer instruc- tion such as lda or sta , a value which never affect its bit state is required. take the following sequence to change these bits contents: (1) store the register contents onto a variable or a data register. (2) change the target bit on the variable or the data register. si- multaneously mask the bit so that its bit state cannot be changed. (see to table 39.) (3) write the value from the variable or the data register to the register using the transfer instruction such as lda or sta. ?to use the auto_set function for an in transfer when the auto_set bit is set to 1, set the fifo to single buffer mode. table 32 bits of which state might be changed owing to software write register name usb endpoint 0 in control register usb endpoint x (x = 1 to 4) in control register usb endpoint x (x = 1 to 4) out control register bit name in_pkt_rdy (b1) data_end (b3) force_stall (b4) in_pkt_rdy (b0) under_run (b1) out_pkt_rdy (b0) over_run (b1) force_stall (b4) data_err (b5) value not affecting state ( note ) 0 0 1 0 1 1 1 1 1 note: writing this value will not change the bit state, because this value cannot be written to the bit by software.
7641 group rev.4.00 aug 28, 2006 page 131 of 135 rej03b0191-0400 frequency synthesizer ? the frequency synthesizer and dc-dc converter must be set up as follows when recovering from a hardware reset: (1) enable the frequency synthesizer after setting the frequency synthesizer related registers (addresses 006c 16 to 006f 16 ). then wait for 2 ms. (2) check the frequency synthesizer lock status bit. if 0 , wait for 0.1 ms and then recheck. (3) when using the usb built-in dc-dc converter, set the usb line driver supply enable bit of the usb control register to 1 . this setting must be done 2 ms or more after the setup described in step (1). the usb line driver current control bit must be set to 0 at this time. (when vcc = 3.3v, the setting explained in this step is not necessary.) (4) after waiting for (c + 1) ms so that the external capacitance pin (ext. cap. pin) can reach approximately 3.3 v, set the usb clock enable bit to 1 . at this time, c equals the ca- pacitance ( f) of the capacitor connected to the ext. cap. pin. for example, if 2.2 f and 0.1 f capacitors are con- nected to the ext. cap. in parallel, the required wait will be (2.3 + 1) ms. (5) after enabling the usb clock, wait for 4 or more cycles, and then set the usb enable bit to 1 . ? bits 6 and 5 of the frequency synthesizer control register (ad- dress 006c 16 ) are initialized to 11 after reset release. make sure to set bits 6 and 5 to 10 after the frequency synthesizer lock status bit goes to 1 . ? when using the frequency synthesized clock function, we recom- mend using the fastest frequency possible of f(x in ) or f(x cin ) as an input clock for the pll. owing to the pll mechanism, the pll controls the speed of multiplied clocks from the source clock. as a result, when the source clock input is lower, the generated clock becomes less stable. this is because more multipliers are needed and the speed control is very rough. higher source clock input generates a stabler clock, as less multipliers are needed and the speed control is more accurate. however, if the input clock frequency is relatively high, the pll clock generator can quickly lock-up the output clock to the source and make the out- put clock very stable. ? set the value of frequency synthesizer multiply register 2 (fsm2) so that the fpin is 1 mhz or higher. dma ? in the memory expansion mode and microprocessor mode, the dma out pin outputs h during a dma transfer. ? do not access the dmac-related registers by using a dmac transfer. the destination address data and the source address data will collide in the dmac internal bus. ? when using the usb fifo as the dma transfer source, make sure that, if you use the auto_set function, short packet data does not get mixed in with the transfer data. ? when setting the dmac channel x enable bit (bit 7 of address 0041 16 ) to 1 , be sure simultaneously to set the dmac channel x transfer initiation source capture register reset bit (bit 6 of ad- dress 0041 16 ) to 1 . if this is not performed, an incorrect data will be transferred at the same time when the dmac is enabled. memory expansion mode & microprocessor mode ? in both memory expansion mode and microprocessor mode, use the ldm instruction or sta instruction to write to port p3 (address 000e 16 ). when using the read-modify-write instruction ( seb in- struction, clb instruction) you will need to map a memory that the cpu can read from and write to. ? in the memory expansion mode, if the internal and external memory areas overlap, the internal memory becomes the valid memory for the overlapping area. when the cpu performs a read or a write operation on this overlapped area, the following things happen: (1) read the cpu reads out the data in the internal memory instead of in the external memory. note that, since the cpu will output a proper read signal, address signal, etc., the memory data at the respective address will appear on the external data bus. (2) write the cpu writes data to both the internal and external memo- ries. ? the wait function is serviceable at accessing an external memory. stop mode ? when the stp instruction is executed, bit 7 of the clock control register (address 001f 16 ) goes to 0 . to return from stop mode, reset ccr7 to 1 . ? when using f syn (set internal system clock select bit (cpma6) to 1 ) as the internal system clock, switch cpma6 to 0 before executing the stp instruction. reset cpma6 after the system re- turns from stop mode and the frequency synthesizer has stabilized. cpma6 does not need to be switched to 0 when using the wit instruction. ? when the stp instruction is being executed, all bits except bit 4 of the timer 123 mode register (address 0029 16 ) are initialized to 0 . it is not necessary to set t123m1 (timer 1 count stop bit) to 0 before executing the stp instruction. after returning from stop mode, reset the timer 1 (address 0024 16 ), timer 2 (address 0025 16 ), and the timer 123 mode register (address 0029 16 ).
7641 group rev.4.00 aug 28, 2006 page 132 of 135 rej03b0191-0400 usage notes oscillator connection notice the built-in feedback register (1 m ? ) and the dumping resistor (400 ? ) is internally connected between pins x in and x out . power source voltage when the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. in a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the power source voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation. power supply pins treatment notice please connect 0.1 f and 4.7 f capacitors in parallel between pins vcc and vss, and pins avss and avcc. these capacitors must be connected as close as possible be- tween the dc supply and gnd pins, and also the analog supply pin and corresponding gnd pin. wiring patterns for these supply and gnd pins must be wider than other signal patterns. these filter capacitors should not be placed near the lpf pins as they will cause noise problems reset pin treatment notice (noise elimination) if the reset input signal rises very slowly, we recommend attaching a capacitor, such as a 1000 pf ceramic capacitor with excellent high frequency characteristics, between the reset pin and the vss pin. please note the following two issues for this capacitor connection. (1) capacitor wiring pattern must be as short as possible (within 20 mm). (2) the user must perform an application level operation test. lpf pin treatment notice all passive components must be located as close as possible to the lpf pin. 0 . 1 f 6 8 0 p f l p f p i n a v s s p i n 1 k ? fig. 111 passive components near lpf pin ?in vcc = 3.3 v operation, connect the ext. cap. pin directly to the vcc pin in order to supply power to the usb transceiver. in addi- tion, you will need to disable the dc-dc converter in this operation (set bit 4 of the usb control register to 0.) if you are using the bus powered supply in vcc = 3.3 v operation, the dc- dc converter must be placed outside the mcu. ?in vcc = 5 v operation, do not connect the external dc-dc con- verter to the ext. cap. pin. use the built-in dc-dc converter by enabling the usb line driver. ?make sure the usb d+/d- lines do not cross any other wires. keep a large gnd area to protect the usb lines. also, make sure you use a usb specification compliant connecter for the connec- tion. x in e n a b l e l o c k f s e l s u s b c 5 e n a b l e u s b c l o c k ( 4 8 m h z ) u s b f c u enable u s b c 7 u s b t r a n s c e i v e r e n a b l e u s b c 7 d c - d c c o n v e r t e r e n a b l e u s b c 4 c u r r e n t m o d e u s b c 3 e x t . c a p . 2 . 2 ? n o t e 1 n o t e s 1 : i n v c c = 3 . 3 v , c o n n e c t t o v c c . i n v c c = 5 v , d o n o t c o n n e c t t h e e x t e r n a l d c - d c c o n v e r t e r t o t h e e x t . c a p p i n . 2 : t h e r e s i s t o r s v a l u e s d e p e n d o n t h e l a y o u t o f t h e p r i n t e d c i r c u i t b o a r d . n o t e 2 fig.112 peripheral circuit avss and avcc pin treatment notice (noise elimination) an insulation connector (ferrite beads) must be connected be- tween avss and vss pins and between avcc and vcc pins. usb transceiver treatment (noise elimination) ? the full-speed usb2.0 specification requires a driver -imped- ance 28 to 44 ?. ? ? ? connect a capacitor between the ext. cap. pin and the vss pin. the capacitor should have a 2.2
7641 group rev.4.00 aug 28, 2006 page 133 of 135 rej03b0191-0400 usb communication in applications requiring high-reliability, we recommend providing the system with protective measures such as usb function initial- ization by software or usb reset by the host to prevent usb communication from being terminated unexpectedly, for example due to external causes such as noise. clock input/output pin wiring (noise elimination) (1) make the wiring for the input/output pins as short as possible. (2) make the wiring across the grounding lead of the capacitor which is connected to an oscillator and the vss pin of the mcu as short as possible (within 20 mm) (3) make sure to isolate the oscillation vss pattern from other pat- terns for oscillation circuit-use only. oscillator wiring (noise elimination) (1) keeping oscillator away from large current signal lines install a microcomputer (and especially an oscillator) as far as possible from signal lines, including usb signal lines, where a cur- rent larger than the tolerance of current value flows. when a large current flows through those signal lines, strong noise occurs be- cause of mutual inductance. (2) installing oscillator away from signal lines where potential levels change frequently install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. terminate unused pins (1) output ports : open (2) input ports : connect each pin to vcc or vss through each resistor of 1 k ? to 10 k ? . ports that permit the selecting of a built-in pull-up or pull-down re- sistor can also use this resistor. as for pins whose potential affects to operation modes such as pins cnvss, int or others, select the vcc pin or the vss pin according to their operation mode. (3) i/o ports : ? set the i/o ports for the input mode and connect them to vcc or vss through each resistor of 1 k ? to 10 k ? . ports that permit the selecting of a built-in pull-up or pull-down re- sistor can also use this resistor. set the i/o ports for the output mode and open them at l or h . ? when opening them in the output mode, the input mode of the initial status remains until the mode of the ports is switched over to the output mode by the program after reset. thus, the potential at these pins is undefined and the power source current may in- crease in the input mode. with regard to an effects on the system, thoroughly perform system evaluation on the user side. ? since the direction register setup may be changed because of a program runaway or noise, set direction registers by program pe- riodically to increase the reliability of program. ? at the termination of unused pins, perform wiring at the shortest possible distance (20 mm or less) from microcomputer pins. electric characteristic differences between mask rom and flash memory version mcus there are differences in electric characteristics, operation margin, noise immunity, and noise radiation between mask rom and flash memory version mcus due to the difference in the manufac- turing processes. when manufacturing an application system with the flash memory version and then switching to use of the mask rom ver- sion, please perform sufficient evaluations for the commercial samples of the mask rom version. data required for mask orders the following are necessary when ordering a mask rom produc- tion: 1. mask rom order confirmation form 2. mark specification form 3. data to be written to rom, in eprom form (three identical cop- ies) or one floppy disk. for the mask rom confirmation and the mark specifications, refer to the renesas technology corp. homepage (http://www.renesas.com).
7641 group rev.4.00 aug 28, 2006 page 134 of 135 rej03b0191-0400 package outline y f * 3 * 1 * 2 1 2 4 2 5 41 64 65 80 in de x m a r k c b p d e h e a e z d z e h d d e t a il f l a 1 a 2 in c l u de trim o ff s et . * note ) * * 2" 1. previous c od e jeita packa g e cod e rene s a s c od e pr q p0080gb- a 80 p 6 n- a mass[t y p. ] 1.6 g p- q fp80-14x20-0.8 0 0 .2 0 .1 5 0 .1 3 0 . 35 0 . 3 m ax n om mi n dim e n s i o n in millim e t e r s sy mbo l 1 9 . 8 d 14.2 14. 0 1 3 . 8 e 2. 8 a 2 23 . 1 22. 8 22. 5 17.1 1 6 . 8 1 6 . 5 3 . 05 a 0 .2 0 . 1 0 0 . 8 0 . 6 0 . 4 l 1 0
7641 group rev.4.00 aug 28, 2006 page 135 of 135 rej03b0191-0400 de t a il f c a l 1 l a 1 a 2 * 2 * 1 f 41 0 2 0 z e e h e d h d 2. 1 . dimen s i o n s " * 1" and " * 2 " note ) dimen s i o n " * 3 " d o e s n ot in c l u de trim o ff s et . previous c od e jeita packa g e cod e rene s a s c od e pl q p0080kb- a 80p6 q - a mass[t y p. ] 0.5 g p-l q fp80-12x12-0.5 0 1. 0 0 .12 5 0 .1 8 1.2 5 1.2 5 0 . 08 0 .2 0 0 .14 5 0 . 09 0 . 25 0 . 20 0 . 15 m ax n om min d im e n s i o n in millim e t e r s sy mbo l r e f e r e n ce 12 .1 12. 0 11. 9 d 12 .1 12. 0 11. 9 e 1 .4 a 1 4.2 14. 0 1 3 . 8 14.2 1 4. 0 13 . 8 1 .7 0 . 2 0 . 1 0 0 . 7 0 . 5 0 . 3 l x 1 0
revision history 7641 group data sheet rev. date description page summary (1/ ) 1.0 04/06/2001 first edition page 1 page 104 page 105 page 145 page 146 2.0 05/17/2001 notes 2 are added. fig.89 is revised: explanation of bits 5 to 7 and notes. fig.90 is revised: explanation of flow chart. usb transceiver treatment line 9 is revised: between the usb d+ pin and usb d- pin, or is deleted. url of mitsubishi mcu technical information homepage is revised: http://www.infomicom.maec.co.jp 3.0 12/27/2001 page 1 page 4 page 6 page 11 page 22 page 31 page 38 page 39 page 42 page 44 page 45 page 46 page 53 page 55 page 75 page 80 page 88 page 91 page 94 pages 102 to 128 page 130 page 131 page 132 operating temperature range is added. table 1 is revised: ext. cap. functions explanation is revised. fig.4 is revised: a- is eliminated. fig.8 is revised: bit 4 explanation of cpma is revised. fig.17 is revised: the symbol of interrupt control register c is corrected. the pin name srd is corrected to srdy. fig.31 is revised: serial i/o as interrupt is eliminated. fig.32 is revised: bit 5 explanation of dmaxm1 is revised. the flag name in section priority is corrected to the dmac channel x (x =0, 1) suspend flag (dxsfi). the explanation of section interrupt transfer mode is revised. some explanations of section usb reception is eliminated. the all usb internal registers addresses in section usb function interrupt is cor- rected to 005f 16 . the explanation of section in_csr is revised. fig.48 is revised: bits 0 and 3 name of out_csr is corrected. fig.70 is revised: bit 4 explanation of cpma is revised. table 10 is revised: avcc and ext. cap. as a parameter is added. table 18 is revised: ext. cap. limits are added. table 20 is revised: test conditions to be determined are eliminated. table 24 is revised: the parameter of t d(wr-db) is revised. the explanation of section flash memory mode is revised. the all usb internal registers addresses in section usb function interrupt is cor- rected to 005f 16 . the explanation of in_pkt_rdy is revised. the explanation of section dma is revised. the explanation of section usb transceiver treatment is added: in vcc = 5 v. 3.1 3/26/2002 page 1 page 7 page 102 page 115 page 133 power source voltage and program/erase voltage of flash memory mode in fea- tures are updated. fig. 5 is revised: m37641f8 is in mass-production status. table 25 is revised. table 28 is revised. one usage note is added: electric characteristic differences between mask rom and flash memory version mcus 4.0 8/28/2006 all pages all pages 38 package names 80p6n-a prqp0080gb-a revised package names 80p6q-a plqp0080kb-a revised usb std. spec. ver.1.1 full-speed usb2.0 specification dmac; (dxcen) (dxhr) 2
revision history 7641 group data sheet rev. date description page summary (2/ ) 4.0 8/28/2006 fig. 47 4: to use the auto_set function .... to single buffer mode. added clock generating circuit; no external resistor is needed .... resistor exists on-chip. no external resistor is needed .... depending on conditions.) fig. 64; pulled up added, note added uart; ?do not update .... data might be output. added usb; ?use the auto_flush bit .... buffer mode., ?to use the auto_set function .... to single buffer mode. added oscillator connection notice; the built-in feedback register (400 ) .... pins x in and x out . the built-in feedback register (1 m ) .... pins x in and x out . power source voltage added usb communication added for the mask rom confirmation .... http://www.infomicom.maec.co.jp/indexe.htm for the mask rom confirmation .... (http://www.renesas.com). package outline revised 54 70 129 130 132 133 134 2
keep safety first in your circuit designs! 1. renesas technology corp. puts the maximum effort into making semiconductor products better and more reliable, but there is a lways the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placeme nt of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement 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renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology 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